{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T19:49:47Z","timestamp":1771703387452,"version":"3.50.1"},"reference-count":15,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2014,12,1]],"date-time":"2014-12-01T00:00:00Z","timestamp":1417392000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Basic Research Program of China","doi-asserted-by":"crossref","award":["2011CBA00602"],"award-info":[{"award-number":["2011CBA00602"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"crossref"}]},{"name":"National Key Scientific and Technological Project","award":["2013ZX01032001-001-003"],"award-info":[{"award-number":["2013ZX01032001-001-003"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,12]]},"DOI":"10.1109\/tvlsi.2013.2296791","type":"journal-article","created":{"date-parts":[[2014,1,31]],"date-time":"2014-01-31T17:51:40Z","timestamp":1391190700000},"page":"2629-2634","source":"Crossref","is-referenced-by-count":4,"title":["A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA"],"prefix":"10.1109","volume":"22","author":[{"given":"Jianfeng","family":"Zhu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Liyang","family":"Pan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yaru","family":"Yan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dong","family":"Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hu","family":"He","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"1","article-title":"Statistical dual-VDD assignment for FPGA interconnect power reduction","author":"yan","year":"2007","journal-title":"Proc Des Autom Test Eur Conf Exhibit"},{"key":"ref11","author":"rabaey","year":"2003","journal-title":"Digital Integrated Circuits A Design Perspective"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2004.1393249"},{"key":"ref13","first-page":"312","article-title":"A flexible power model for FPGAs","author":"poon","year":"2002","journal-title":"Proc Int Conf Field Program Logic Appl"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508150"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.826551"},{"key":"ref4","first-page":"145","article-title":"A dual-VDD low power FPGA architecture","author":"gayasen","year":"2004","journal-title":"Proc Int Conf Field Program Logic Appl"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.857180"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/92.953496"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/4.839927"},{"key":"ref8","first-page":"10718","article-title":"Concurrent sizing, VDD and Vth assignment for low-power design","author":"srivastava","year":"2004","journal-title":"Proc Des Autom Test Eur Conf"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"200","DOI":"10.1145\/1013235.1013287","article-title":"A New Algorithm for Improved VDD Assignment in Low Power Dual VDD Systems","author":"kulkarni","year":"2004","journal-title":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design LPE"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065769"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996767"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2002.1106788"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6963544\/06714579.pdf?arnumber=6714579","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,3,24]],"date-time":"2022-03-24T20:20:14Z","timestamp":1648153214000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6714579"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,12]]},"references-count":15,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2296791","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,12]]}}}