{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,4]],"date-time":"2022-04-04T05:03:12Z","timestamp":1649048592113},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,1]]},"DOI":"10.1109\/tvlsi.2014.2303809","type":"journal-article","created":{"date-parts":[[2014,2,26]],"date-time":"2014-02-26T19:20:04Z","timestamp":1393442404000},"page":"213-217","source":"Crossref","is-referenced-by-count":5,"title":["Recursive Approach to the Design of a Parallel Self-Timed Adder"],"prefix":"10.1109","volume":"23","author":[{"given":"Mohammed Ziaur","family":"Rahman","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lindsay","family":"Kleeman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohammad Ashfak","family":"Habib","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","author":"rahman","year":"2013","journal-title":"A delay matched approach for the design of asynchronous sequential circuits"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICIT.2008.18"},{"key":"ref10","author":"weste","year":"2005","journal-title":"CMOS VLSI Design A Circuits and Systems Perspective"},{"key":"ref6","author":"tinder","year":"2009","journal-title":"Asynchronous Sequential Machine Design and Analysis A Comprehensive Development of the Design and Analysis of Clock-Independent State Machines and Systems"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2006.1669377"},{"key":"ref5","author":"riedel","year":"2004","journal-title":"Cyclic Combinational Circuits"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2002.805631"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/12.863035"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/4.309908"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3385-3"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:19960704"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.106"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7014337\/06748987.pdf?arnumber=6748987","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:04:20Z","timestamp":1642003460000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6748987"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,1]]},"references-count":12,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2303809","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,1]]}}}