{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,20]],"date-time":"2026-02-20T17:54:47Z","timestamp":1771610087274,"version":"3.50.1"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2015,2,1]],"date-time":"2015-02-01T00:00:00Z","timestamp":1422748800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003050","name":"METI","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100003050","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100003051","name":"NEDO","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100003051","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1109\/tvlsi.2014.2304733","type":"journal-article","created":{"date-parts":[[2014,2,26]],"date-time":"2014-02-26T19:20:04Z","timestamp":1393442404000},"page":"356-368","source":"Crossref","is-referenced-by-count":23,"title":["An 8 bit 0.3\u20130.8 V 0.2\u201340 MS\/s 2-bit\/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS"],"prefix":"10.1109","volume":"23","author":[{"given":"Kentaro","family":"Yoshioka","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Akira","family":"Shikata","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ryota","family":"Sekimoto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tadahiro","family":"Kuroda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroki","family":"Ishikuro","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref31","first-page":"92","article-title":"A 3.2 fJ\/c.-s. 0.35 V 10b 100 KS\/s SAR ADC in 90 nm CMOS","author":"tai","year":"2012","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2191184"},{"key":"ref10","first-page":"1","article-title":"A 7b 1 GS\/s 7.2 mW Nonbinary 2b\/cycle SAR ADC with register-to-DAC direct control","author":"hong","year":"2012","journal-title":"Proc IEEE CICC"},{"key":"ref11","first-page":"188","article-title":"A 0.024 mm2 8b 400 MS\/s SAR ADC with 2b\/Cycle and Resistive DAC in 65 nm CMOS","author":"wei","year":"2011","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243803"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006315"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E96.A.443"},{"key":"ref15","first-page":"328","article-title":"A 65 nm CMOS comparator with modified latch to achieve 7 GHz\/1.3 mW at 1.2 V and 700 MHz\/47-W at 0.6 V","author":"goll","year":"2009","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref16","first-page":"238","article-title":"A 6-bit 50-MS\/s threshold configuring SAR ADC in 90-nm digital CMOS","author":"nuzzo","year":"2009","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2061611"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2008.4708780"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2108125"},{"key":"ref28","first-page":"190","article-title":"A resolution-reconfigurable 5-to-10b, 0.4-to-1 V power scalable SAR ADC","author":"yip","year":"2011","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref4","first-page":"472","article-title":"A 7-to-10b 0-to-4 MS\/s flexible SAR ADC with 6.5-to-16 fJ\/conversion-step","author":"harpe","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref27","first-page":"384","article-title":"A 10 b 50 MS\/s 820 $\\mu{\\rm W}$ SAR ADC with on-chip digital calibration","author":"yoshioka","year":"2010","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185352"},{"key":"ref6","first-page":"471","article-title":"A 40 nm 50 S\/s-8 MS\/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator","author":"sekimoto","year":"2011","journal-title":"Proc IEEE ESSCIRC"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042254"},{"key":"ref5","first-page":"270","article-title":"A 2.2\/2.7 fJ\/conversion-step 10\/12b 40 kS\/s SAR ADC with data-driven noise reduction","author":"harpe","year":"2013","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref8","first-page":"381","article-title":"An 8bit 0.35–0.8 V 0.5–30 MS\/s 2-bit\/step SAR ADC with wide range threshold configuring comparator","author":"yoshioka","year":"2012","journal-title":"Proc IEEE ESSCIRC"},{"key":"ref7","first-page":"84","article-title":"A 2.8 GS\/s 44.6 mW time-interleaved ADC achieving 50.9 dB SNDR and 3 dB effective resolution bandwidth of 1.5 GHz in 65 nm CMOS","author":"stepanovic","year":"2012","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2043893"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2012329"},{"key":"ref1","first-page":"6","article-title":"The swarm at the edge of the cloud—A new perspective on wireless","author":"rabaey","year":"2011","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref20","first-page":"31","article-title":"A 0.16 pJ\/conversion-step 2.5 mW 1.25 GS\/s 4b ADC in a 90 nm digital CMOS process","author":"van der plas","year":"2006","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref22","first-page":"26","article-title":"A 6b 3 GS\/s 11 mW fully dynamic flash ADC in 40 nm CMOS with reduced number of comparators","author":"shu","year":"2012","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2012449"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.917991"},{"key":"ref23","author":"razavi","year":"2001","journal-title":"Design of Analog CMOS Integrated Circuits"},{"key":"ref26","first-page":"36","article-title":"0.5 V image processor with 563 GOPS\/W SIMD and 32-bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40 nm CMOS","author":"nomura","year":"2013","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref25","first-page":"1","article-title":"A 7b 1.4 GS\/s ADC with offset drift suppression techniques for one-time calibration","author":"nakajima","year":"2012","journal-title":"Proc IEEE CICC"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7027264\/06748934.pdf?arnumber=6748934","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:41:24Z","timestamp":1642005684000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6748934"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2]]},"references-count":31,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2304733","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,2]]}}}