{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,4]],"date-time":"2022-04-04T12:45:01Z","timestamp":1649076301170},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2015,2,1]],"date-time":"2015-02-01T00:00:00Z","timestamp":1422748800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"EPSRC for Globally Asynchronous Elastic Logic Synthesis","award":["EP\/I038551\/1"],"award-info":[{"award-number":["EP\/I038551\/1"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1109\/tvlsi.2014.2306176","type":"journal-article","created":{"date-parts":[[2014,3,3]],"date-time":"2014-03-03T19:03:15Z","timestamp":1393873395000},"page":"292-305","source":"Crossref","is-referenced-by-count":0,"title":["Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging"],"prefix":"10.1109","volume":"23","author":[{"given":"James S.","family":"Guido","sequence":"first","affiliation":[]},{"given":"Alexandre","family":"Yakovlev","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2001.914083"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ACSD.2010.11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICM.2010.5696176"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/4.16314"},{"key":"ref14","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-642-55989-1","volume":"8","author":"cortadella","year":"2002","journal-title":"Logic Synthesis for Asynchronous Controllers and Interfaces"},{"key":"ref15","first-page":"1","article-title":"Logical effort: Designing for speed on the back of an envelope","author":"sutherland","year":"1991","journal-title":"Proc Univ California\/Santa Cruz Conf Adv Res VLSI"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/s10703-006-7843-9"},{"key":"ref17","first-page":"237","article-title":"Synthesis of asynchronous VLSI circuits","volume":"2","author":"martin","year":"1990","journal-title":"Formal Methods VLSI Des"},{"key":"ref18","author":"chu","year":"1987","journal-title":"Synthesis of self-timed VLSI circuits from graph-theoretic specifications"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1995.470376"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2005.10"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.831476"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1002\/9780470517147"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2006.12"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/4.341740"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1997.628884"},{"key":"ref9","author":"van berkel","year":"1992","journal-title":"Handshake circuits An intermediary between communicating processes and VLSI"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/5.929649"},{"key":"ref20","first-page":"315","article-title":"Petrify: A tool for manipulating concurrent specifications and synthesis of asynchronous controllers","volume":"80","author":"cortadella","year":"1997","journal-title":"IEICE Trans Inf Syst"},{"key":"ref22","author":"rabaey","year":"2003","journal-title":"Digital Integrated Circuits A Design Perspective"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-73094-1_30"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/4.982426"},{"key":"ref23","first-page":"204","article-title":"A theory of asynchronous circuits","author":"muller","year":"1959","journal-title":"Proc Int Symp Theory Switching"},{"key":"ref25","author":"sokolov","year":"2006","journal-title":"Automated synthesis of asynchronous circuits using direct mapping for control and data paths"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7027264\/06754196.pdf?arnumber=6754196","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:41:24Z","timestamp":1642005684000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6754196"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2]]},"references-count":25,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2306176","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,2]]}}}