{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,10]],"date-time":"2024-08-10T02:15:36Z","timestamp":1723256136451},"reference-count":26,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2015,2,1]],"date-time":"2015-02-01T00:00:00Z","timestamp":1422748800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1109\/tvlsi.2014.2309439","type":"journal-article","created":{"date-parts":[[2014,3,25]],"date-time":"2014-03-25T18:09:06Z","timestamp":1395770946000},"page":"407-412","source":"Crossref","is-referenced-by-count":1,"title":["Functional Constraint Extraction From Register Transfer Level for ATPG"],"prefix":"10.1109","volume":"23","author":[{"given":"Christelle","family":"Hobeika","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Claude","family":"Thibeault","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jean-Francois","family":"Boland","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"398","DOI":"10.1109\/DFTVS.2005.49","article-title":"On generating pseudo-functional delay fault tests for scan designs","author":"zhang","year":"2005","journal-title":"Proc 20th IEEE Int Symp Defect Fault Tolerance VLSI Syst"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/43.658570"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1992.227793"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639687"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1999.782022"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2000.889552"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998380"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"111","DOI":"10.1145\/982962.964011","article-title":"Parsing expression grammars: A recognition-based syntactic foundation","volume":"39","author":"ford","year":"2004","journal-title":"ACM SIGPLAN Notices"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2010.5603786"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-007-5024-4"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MNRC.2008.4683396"},{"key":"ref3","article-title":"Functional verification study","year":"2007","journal-title":"Industry Study (Conjunction with Mentor Graphics)"},{"key":"ref6","first-page":"166","article-title":"Constraint extraction for pseudo-functional scan-based delay testing","volume":"1","author":"lu","year":"2005","journal-title":"Proc Asia South Pacific Des Autom Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.1999.761213"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.1995.580747"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"1535","DOI":"10.1109\/TCAD.2005.857379","article-title":"Pseudo-functional testing","volume":"25","author":"lu","year":"2006","journal-title":"IEEE Trans Computer-Aided Design Integr Circuits Syst"},{"key":"ref2","year":"1998","journal-title":"Verification Reuse Methodology Essential Elements for Verification Productivity Gain"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DELTA.2008.25"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2009.5290420"},{"key":"ref20","author":"davidson","year":"1999","journal-title":"Characteristics of the ITC'99 benchmark circuits"},{"key":"ref22","article-title":"Hardware design verification, simulation and formal method based approaches","author":"lam","year":"2005","journal-title":"Prentice-Hall Modern Semiconductor Design Series"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.134"},{"key":"ref24","author":"christelle","year":"2011","journal-title":"M&#x00E9;thodologie de v&#x00E9;rification automatique bas&#x00E9;e sur l'utilisation des tests strucurels de transition avec insertion des registres &#x00E0; balayage"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/296333.296347"},{"key":"ref26","author":"hobeika","year":"2013","journal-title":"Technical Report Functional Constraint Extraction from RTL for ATPG"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-6000-9_4"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7027264\/06778092.pdf?arnumber=6778092","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:41:24Z","timestamp":1642005684000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6778092"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2]]},"references-count":26,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2309439","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,2]]}}}