{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,19]],"date-time":"2025-11-19T06:54:54Z","timestamp":1763535294580},"reference-count":46,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2015,3,1]],"date-time":"2015-03-01T00:00:00Z","timestamp":1425168000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Center for Integrated Smart Sensors through the Ministry of Science, ICT, and Future Planning as the Global Frontier Project","award":["CISS-2013073718"],"award-info":[{"award-number":["CISS-2013073718"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,3]]},"DOI":"10.1109\/tvlsi.2014.2311798","type":"journal-article","created":{"date-parts":[[2014,3,31]],"date-time":"2014-03-31T18:05:15Z","timestamp":1396289115000},"page":"520-533","source":"Crossref","is-referenced-by-count":12,"title":["Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM\/MRAM L2 Cache"],"prefix":"10.1109","volume":"23","author":[{"given":"Seunghan","family":"Lee","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kyungsu","family":"Kang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chong-Min","family":"Kyung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/781027.781048"},{"key":"ref38","first-page":"73","article-title":"Processor caches built using multi-level spin-transfer torque RAM cells","author":"chen","year":"2011","journal-title":"Proc ISLPED"},{"key":"ref33","first-page":"23","article-title":"PTLsim: A cycle accurate full system x86-64 microarchitectural simulator","author":"yourst","year":"2007","journal-title":"Proc Int Symp ISPASS"},{"key":"ref32","author":"burger","year":"1996","journal-title":"Evaluating future microprocessors The Simplescalar tool set"},{"key":"ref31","first-page":"459","article-title":"A novel non-volatile memory with spin torque transfer magnetization switching: Spin-RAM","author":"hosomi","year":"2005","journal-title":"Proc Int Symp IEDM"},{"key":"ref30","author":"tarjan","year":"2006","journal-title":"CACTI 4 0"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.136"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/1450095.1450125"},{"key":"ref35","year":"2014","journal-title":"Performance application programming interface"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.876103"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333709"},{"key":"ref40","first-page":"1","article-title":"Integrating complete-system and user-level performance\/power simulators: The SimWattch approach","author":"chen","year":"2003","journal-title":"Proc ISPASS"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333717"},{"key":"ref12","first-page":"45","article-title":"Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design","author":"chen","year":"2012","journal-title":"Proc DATE"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2105513"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228477"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1269096"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2010.22"},{"key":"ref17","first-page":"1","article-title":"An energy-efficient 3D CMP design with fine-grained voltage scaling","author":"zhao","year":"2011","journal-title":"Proc DATE"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2011.5770786"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.850860"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1147\/sj.92.0078"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798236"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024738"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"1479","DOI":"10.1109\/TCAD.2008.925793","article-title":"Three-dimensional chip-multiprocessor run-time thermal management","volume":"27","author":"zhu","year":"2008","journal-title":"IEEE Trans Comput -Aided Des Integr Circuits Syst"},{"key":"ref29","first-page":"469","article-title":"McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures","author":"ahn","year":"2009","journal-title":"Proc Int Symp Microarchit"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2059290"},{"key":"ref8","first-page":"611","article-title":"Analysis and runtime management of 3D systems with stacked DRAM for boosting energy efficiency","author":"meng","year":"2012","journal-title":"Proc DATE"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2009.27"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2035509"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.13"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"ref46","year":"2010","journal-title":"Intel Core i5 Mobile Processor Series"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2101371"},{"key":"ref45","year":"2007","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref22","year":"2014","journal-title":"SPEC"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1063\/1.4811130"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1287\/opre.11.3.399"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2011.5873205"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809463"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.125"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1137\/1019044"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.18"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7046457\/06781003.pdf?arnumber=6781003","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:41:01Z","timestamp":1642005661000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6781003"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,3]]},"references-count":46,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2311798","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,3]]}}}