{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T16:57:11Z","timestamp":1775667431440,"version":"3.50.1"},"reference-count":26,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2015,5,1]],"date-time":"2015-05-01T00:00:00Z","timestamp":1430438400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Ministry of Economic Affairs in Taiwan","award":["100-EC-17-A-01-S1-124"],"award-info":[{"award-number":["100-EC-17-A-01-S1-124"]}]},{"DOI":"10.13039\/501100001868","name":"National Science Council of Taiwan","doi-asserted-by":"crossref","award":["NSC 102-2218-E-009-025"],"award-info":[{"award-number":["NSC 102-2218-E-009-025"]}],"id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Ministry of Education in Taiwan under ATU Program"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,5]]},"DOI":"10.1109\/tvlsi.2014.2318518","type":"journal-article","created":{"date-parts":[[2014,5,8]],"date-time":"2014-05-08T14:08:06Z","timestamp":1399558086000},"page":"958-962","source":"Crossref","is-referenced-by-count":28,"title":["A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist"],"prefix":"10.1109","volume":"23","author":[{"given":"Chien-Yu","family":"Lu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ching-Te","family":"Chuang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shyh-Jye","family":"Jou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ming-Hsien","family":"Tu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ya-Ping","family":"Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chung-Ping","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paul-Sen","family":"Kan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Huan-Shun","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kuen-Di","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yung-Shin","family":"Kao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908005"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032493"},{"key":"ref12","first-page":"225","article-title":"A 45 nm 0.5 V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier","author":"sinangil","year":"2009","journal-title":"Proc IEEE Asian Solid State Circuits Conf"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.914328"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2109440"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2011972"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164009"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2102571"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2071690"},{"key":"ref19","first-page":"158","article-title":"A 45 nm 0.6 V cross-point 8T SRAM with negative biased read\/write assist","author":"yabuuchi","year":"2009","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.877276"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.852162"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2020201"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2091321"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2085970"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.917509"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2035453"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001872"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.2007.4547603"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2042086"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2231017"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2187474"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2009.2015312"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2010.5488826"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2029114"},{"key":"ref25","first-page":"46","article-title":"A 0.7 V single-supply SRAM with 0.495 $\\mu $ m $^{2}$ cell in 65 nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme","author":"kushida","year":"2008","journal-title":"Proc IEEE Symp VLSI Circuits"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7091984\/06812218.pdf?arnumber=6812218","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:40:57Z","timestamp":1641987657000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6812218"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5]]},"references-count":26,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2318518","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,5]]}}}