{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,7]],"date-time":"2025-10-07T08:48:44Z","timestamp":1759826924384,"version":"3.37.3"},"reference-count":17,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2015,5,1]],"date-time":"2015-05-01T00:00:00Z","timestamp":1430438400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1217076"],"award-info":[{"award-number":["CCF-1217076"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,5]]},"DOI":"10.1109\/tvlsi.2014.2319192","type":"journal-article","created":{"date-parts":[[2014,7,16]],"date-time":"2014-07-16T14:51:26Z","timestamp":1405522286000},"page":"963-967","source":"Crossref","is-referenced-by-count":17,"title":["Design of Efficient Content Addressable Memories in High-Performance FinFET Technology"],"prefix":"10.1109","volume":"23","author":[{"given":"Debajit","family":"Bhattacharya","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ajay N.","family":"Bhoj","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Niraj K.","family":"Jha","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MCD.2004.1263404"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/16.887014"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2227850"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601953"},{"key":"ref14","first-page":"19.5.1","article-title":"High-performance symmetric-gate and CMOS-compatible V $_{t}$ asymmetric-gate FinFET devices","author":"kedzierski","year":"2001","journal-title":"Proc IEEE IEDM"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2227848"},{"journal-title":"Sentaurus TCAD Tool Suite","year":"2012","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VTSA.2005.1497065"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831433"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818139"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.895879"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.808156"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2011.2175359"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2252031"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.845554"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864128"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MCD.2003.1175108"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7091984\/06857432.pdf?arnumber=6857432","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:40:57Z","timestamp":1641987657000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6857432"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5]]},"references-count":17,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2319192","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2015,5]]}}}