{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T14:54:38Z","timestamp":1761663278845},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2015,4,1]],"date-time":"2015-04-01T00:00:00Z","timestamp":1427846400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Kamin program"},{"name":"Chief Scientist of the Ministry of Economy, Israel"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,4]]},"DOI":"10.1109\/tvlsi.2014.2320154","type":"journal-article","created":{"date-parts":[[2014,6,4]],"date-time":"2014-06-04T18:05:02Z","timestamp":1401905102000},"page":"702-711","source":"Crossref","is-referenced-by-count":25,"title":["Randomized Multitopology Logic Against Differential Power Analysis"],"prefix":"10.1109","volume":"23","author":[{"given":"Moshe","family":"Avital","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hadar","family":"Dagan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Osnat","family":"Keren","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alexander","family":"Fish","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","first-page":"443","article-title":"A unified framework for the analysis of side-channel key recovery attacks","author":"standaert","year":"2009","journal-title":"Advances in Cryptology-Eurocrypt"},{"key":"ref32","first-page":"13","article-title":"Template attacks","author":"chari","year":"2002","journal-title":"CHES"},{"key":"ref31","author":"miller","year":"2009","journal-title":"Advanced Encryption Standard"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1049\/iet-ifs.2010.0096"},{"key":"ref36","first-page":"427","article-title":"Information theoretic evaluation of side-channel resistant logic styles","volume":"4727","author":"mac","year":"2007","journal-title":"CHES"},{"key":"ref35","year":"1988","journal-title":"National Institute of Standards and Technology"},{"key":"ref34","author":"rabaey","year":"2004","journal-title":"Digital Integrated Circuits A Design Perspective"},{"key":"ref10","author":"mangard","year":"2007","journal-title":"Power Analysis Attacks Revealing the Secrets of Smart Cards"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IITA.2009.212"},{"key":"ref12","article-title":"Cryptographic unit and method for operating a crytographic unit","author":"gammel","year":"2010"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"292","DOI":"10.1007\/3-540-48059-5_25","article-title":"Resistance against differential power analysis for elliptic curve cryptosystems","author":"coron","year":"1999","journal-title":"Cryptographic Hardware and Embedded Systems"},{"key":"ref14","first-page":"231","article-title":"On Boolean and arithmetic masking against differential power analysis","author":"coron","year":"2000","journal-title":"Proc 2nd Int Workshop CHES"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICSICT.2010.5667769"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2010.5774887"},{"key":"ref17","first-page":"293","article-title":"On second-order differential power analysis","volume":"3659","author":"joye","year":"2005","journal-title":"Proc 7th Int Workshop CHES"},{"key":"ref18","first-page":"403","article-title":"A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards","author":"tiri","year":"2002","journal-title":"Proceedings of the 28th European Solid-State Circuits Conference ESSCIRC"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268856"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4542175"},{"key":"ref4","author":"stinson","year":"2006","journal-title":"Cryptography Theory and Practice"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-23951-9_15"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1002\/9780470665121"},{"key":"ref6","first-page":"104","author":"kocher","year":"1996","journal-title":"Timing Attacks on Implementations of Diffie-Hellman RSA DSS and Other Systems"},{"key":"ref29","first-page":"109","article-title":"A formal study of power variability issues and side-channel attacks for nanoscale devices","author":"renauld","year":"2011","journal-title":"Advances in Cryptology-Eurocrypt"},{"key":"ref5","first-page":"388","article-title":"Differential power analysis","author":"kocher","year":"1999","journal-title":"Proc 16th Annu Int Cryptol Conf Adv Cryptol"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-011-0006-y"},{"key":"ref7","first-page":"157","article-title":"Successfully attacking masked AES hardware implementations","volume":"3659","author":"mangard","year":"2005","journal-title":"Proc 7th Int Workshop CHES"},{"key":"ref2","author":"rankl","year":"2004","journal-title":"Smart Card Handbook"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2002.1004593"},{"key":"ref1","author":"zhang","year":"2010","journal-title":"RFID and Sensor Networks Architectures Protocols Security and Integrations"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870913"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea2010098"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034081"},{"key":"ref24","doi-asserted-by":"crossref","first-page":"81","DOI":"10.1007\/978-3-540-74735-2_6","article-title":"Evaluation of the masked logic style MDPL on a prototype chip","volume":"4727","author":"popp","year":"2007","journal-title":"CHES (Lecture Notes in Computer Science)"},{"key":"ref23","first-page":"172","article-title":"Masked dual-rail pre-charge logic: DPA-resistance without routing constraints","author":"mangard","year":"2005","journal-title":"Proc 7th Int Workshop CHES"},{"key":"ref26","first-page":"232","article-title":"Three-phase dual-rail pre-charge logic","author":"bucci","year":"2006","journal-title":"Proc 8th Int CHES"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea3040300"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7063292\/06825857.pdf?arnumber=6825857","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:41:46Z","timestamp":1642005706000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6825857"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,4]]},"references-count":36,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2320154","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,4]]}}}