{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:16Z","timestamp":1740133276616,"version":"3.37.3"},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2015,5,1]],"date-time":"2015-05-01T00:00:00Z","timestamp":1430438400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001868","name":"National Science Council of Taiwan","doi-asserted-by":"crossref","award":["NSC 98-2221-E-260-026"],"award-info":[{"award-number":["NSC 98-2221-E-260-026"]}],"id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,5]]},"DOI":"10.1109\/tvlsi.2014.2320761","type":"journal-article","created":{"date-parts":[[2014,5,14]],"date-time":"2014-05-14T14:02:04Z","timestamp":1400076124000},"page":"856-868","source":"Crossref","is-referenced-by-count":2,"title":["Range Unlimited Delay-Interleaving and -Recycling Clock Skew Compensation and Duty-Cycle Correction Circuit"],"prefix":"10.1109","volume":"23","author":[{"given":"Yi-Ming","family":"Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shih-Nung","family":"Wei","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2107171"},{"key":"ref11","first-page":"19","article-title":"A 0.35 V, 100 MHz, 0.19 $\\mu $ W\/MHz, 3-locking-cycle all digital delay locked loop with asynchronous-deskewing technology in 55 nm CMOS technology","author":"cheng","year":"2011","journal-title":"Proc Int Symp Integr Circuits"},{"journal-title":"TSMC 0 18 UM Mixed-signal\/RF General Purpose MiM AL 1P6M 1 8\/3 3V Process Digests","year":"2010","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/4.974545"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2021447"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.885396"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2182216"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2158731"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.910566"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2011.6085073"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2047994"},{"journal-title":"Integrated Circuit Design","year":"2010","author":"weste","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2186722"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7091984\/06815790.pdf?arnumber=6815790","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:40:57Z","timestamp":1641987657000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6815790"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5]]},"references-count":13,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2320761","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2015,5]]}}}