{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:06:37Z","timestamp":1761581197816},"reference-count":20,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2015,4,1]],"date-time":"2015-04-01T00:00:00Z","timestamp":1427846400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,4]]},"DOI":"10.1109\/tvlsi.2014.2320912","type":"journal-article","created":{"date-parts":[[2014,5,19]],"date-time":"2014-05-19T18:04:53Z","timestamp":1400522693000},"page":"609-618","source":"Crossref","is-referenced-by-count":11,"title":["Unipolar Logic Gates Based on Spatial Wave-Function Switched FETs"],"prefix":"10.1109","volume":"23","author":[{"given":"Supriya","family":"Karmakar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"John A.","family":"Chandy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Faquir C.","family":"Jain","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/s11664-011-1667-0"},{"key":"ref11","article-title":"Circuit model of SWSFET to implement multi-valued logic","author":"karmakar","year":"2012","journal-title":"Proc 21st CMOC Symp"},{"key":"ref12","article-title":"Implementation of unipolar inverter based on spatial wave-function switched (SWS) FET","author":"karmakar","year":"2012","journal-title":"Proc IEEE Lester Eastman Conf High Perform Devices"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.4313\/TEEM.2011.12.5.175"},{"key":"ref14","first-page":"464","article-title":"A novel design for highly compact low power area efficient 1-bit full adders","volume":"4","author":"khatoon","year":"2012","journal-title":"International Journal of Advanced Engineering Technology"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.1993.378095"},{"key":"ref16","first-page":"53","article-title":"A hybrid radix-4\/radix-8 low power, high speed multiplier architecture for wide bit widths","author":"cherkauer","year":"1996","journal-title":"Proc IEEE ISCAS"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1155\/2013\/495354"},{"key":"ref18","first-page":"1639","article-title":"A design of modified 64 bit wallace multiplier using 45 nm technology","volume":"5","author":"sunilkumar","year":"2013","journal-title":"Int J Eng Technol"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.4236\/cs.2013.42027"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1063\/1.336109"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.1994.302201"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/S0038-1101(03)00268-5"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/BFb0107882"},{"key":"ref8","first-page":"61","article-title":"A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 $\\mu $ m $^2$ SRAM cell","author":"thompson","year":"2002","journal-title":"IEEE IEDM Tech Dig"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-009-0167-9"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/16.925221"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/16.40918"},{"key":"ref9","first-page":"247","article-title":"A 45 nm logic technology with high- $k+$ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging","author":"mistry","year":"2007","journal-title":"IEEE IEDM Tech Dig"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/CONECCT.2014.6740358"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7063292\/06818407.pdf?arnumber=6818407","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:41:46Z","timestamp":1642005706000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6818407"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,4]]},"references-count":20,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2320912","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,4]]}}}