{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,22]],"date-time":"2026-04-22T20:06:19Z","timestamp":1776888379743,"version":"3.51.2"},"reference-count":26,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2015,5,1]],"date-time":"2015-05-01T00:00:00Z","timestamp":1430438400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/OAPA.html"}],"funder":[{"DOI":"10.13039\/100004361","name":"Texas Instruments","doi-asserted-by":"crossref","id":[{"id":"10.13039\/100004361","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,5]]},"DOI":"10.1109\/tvlsi.2014.2321761","type":"journal-article","created":{"date-parts":[[2014,5,23]],"date-time":"2014-05-23T19:03:05Z","timestamp":1400871785000},"page":"916-925","source":"Crossref","is-referenced-by-count":17,"title":["Built-in Self-Calibration and Digital-Trim Technique for 14-Bit SAR ADCs Achieving \u00b11 LSB INL"],"prefix":"10.1109","volume":"23","author":[{"given":"Shankar","family":"Thirunakkarasu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bertan","family":"Bakkaloglu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"A\/D converter with charge redistribution DAC and split summation of main and correcting DAC outputs","author":"timko","year":"1997"},{"key":"ref11","article-title":"Self-calibration method for capacitors in a monolithic integrated circuit","author":"welland","year":"1987"},{"key":"ref12","article-title":"Self-calibration circuit for capacitance mismatch","author":"chen","year":"2007"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/31.1814"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1999.780725"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2123590"},{"key":"ref16","article-title":"Capacitor calibration in SAR converter","author":"leung","year":"2005"},{"key":"ref17","article-title":"Method for search and matching of capacitors for a digital to analog converter of an SAR analog to digital converter","author":"chowdhury","year":"2007"},{"key":"ref18","article-title":"System and apparatus for digitally calibrating capacitors in an analog-to-digital converter using successive approximation","author":"munoz","year":"2002"},{"key":"ref19","first-page":"421","article-title":"A switched-capacitor DAC with analog mismatch correction","author":"moon","year":"2000","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.806257"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.813217"},{"key":"ref6","first-page":"492","author":"johns","year":"1999","journal-title":"Analog Integrated Circuit Design"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1975.1050629"},{"key":"ref8","article-title":"On board self-calibration of analog-to-digital and digital-to-analog converters","author":"tan","year":"1983"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCDG.2012.6360003"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.813296"},{"key":"ref9","first-page":"384","article-title":"A 10-b 50-MS\/s 820- $\\mu $ W SAR ADC with on-chip digital calibration","author":"yoshioka","year":"2010","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.897157"},{"key":"ref20","article-title":"Error correction architecture to increase speed and relax current drive requirements of SAR ADC","author":"srinivasan","year":"2004"},{"key":"ref22","first-page":"176","article-title":"A 1.2 V 10 b 20 MSample\/s non-binary successive approximation ADC in 0.13 $\\mu $ m CMOS","author":"kuttner","year":"2002","journal-title":"Proc IEEE ISSCC"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1986.1052644"},{"key":"ref24","first-page":"386","article-title":"A 10 b 100 MS\/s 1.13 mW SAR ADC with binary-scaled error compensation","author":"liu","year":"2010","journal-title":"IEEE ISSCC Dig Tech Paper"},{"key":"ref23","article-title":"Non-binary capacitor array calibration for a high performance successive approximation analog-to-digital converter","author":"gan","year":"2003"},{"key":"ref26","article-title":"Differential input successive approximation analog to digital converter with common mode rejection","author":"mueck","year":"2008"},{"key":"ref25","article-title":"Programmable input range ADC","author":"kearney","year":"2005"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7091984\/06820772.pdf?arnumber=6820772","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:28:54Z","timestamp":1642004934000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6820772"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5]]},"references-count":26,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2321761","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,5]]}}}