{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:16Z","timestamp":1740133276777,"version":"3.37.3"},"reference-count":37,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2015,5,1]],"date-time":"2015-05-01T00:00:00Z","timestamp":1430438400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1320401"],"award-info":[{"award-number":["CCF-1320401"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,5]]},"DOI":"10.1109\/tvlsi.2014.2325551","type":"journal-article","created":{"date-parts":[[2014,6,19]],"date-time":"2014-06-19T12:44:54Z","timestamp":1403181894000},"page":"869-878","source":"Crossref","is-referenced-by-count":0,"title":["Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips"],"prefix":"10.1109","volume":"23","author":[{"given":"Xiang","family":"Qiu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Malgorzata","family":"Marek-Sadowska","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wojciech P.","family":"Maly","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2005.859612"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/EPTC.2006.342763"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2012.6249092"},{"year":"0","key":"ref30"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/VDAT.2010.5496640"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/92.974905"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223159"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2008.4483978"},{"article-title":"Complementary vertical transistors","year":"2008","author":"maly","key":"ref10"},{"key":"ref11","first-page":"145","article-title":"Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration","author":"maly","year":"2011","journal-title":"Proc 18th Int Conf MIXDES"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2008.4751916"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2293539"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2330667.2330673"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2013.6575912"},{"key":"ref16","first-page":"121","article-title":"A compact model of VeSFET capacitances","author":"kasprowicz","year":"2011","journal-title":"Proc 18th Int Conf MIXDES"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"954","DOI":"10.1145\/1278480.1278715","article-title":"opc-free and minimally irregular ic design style","author":"maly","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.876103"},{"key":"ref19","first-page":"165","article-title":"Compact modeling and SPICE-based simulation for electrothermal analysis of multilevel ULSI interconnects","author":"chiang","year":"2001","journal-title":"Proc IEEE\/ACM ICCAD"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1063\/1.1481958"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"year":"0","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.879797"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2408776.2408796"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISCE.2009.5156918"},{"key":"ref5","first-page":"365","article-title":"Dark silicon and the end of multicore scaling","author":"esmaeilzadeh","year":"2011","journal-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2008.4546911"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1115\/1.1839582"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2006.870340"},{"article-title":"Integrated circuit device, system, and method of fabrication","year":"2009","author":"maly","key":"ref9"},{"article-title":"Self-heating and scaling of thin body transistors","year":"2004","author":"pop","key":"ref1"},{"key":"ref20","first-page":"846","article-title":"High density interconnect at 10 $\\mu$ m pitch with mechanically keyed Cu\/Sn-Cu and Cu-Cu bonding for 3-D integration","author":"reed","year":"2010","journal-title":"Proc 60th ECTC"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1117\/12.382289"},{"key":"ref21","first-page":"1","article-title":"Electrical, thermal and mechanical impact of 3D TSV and 3D stacking technology on advanced CMOS devices&#x2014;Technology directions","author":"beyne","year":"2012","journal-title":"Proc IEEE 3DIC"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2000.852648"},{"key":"ref23","first-page":"151","article-title":"Vertical-slit field-effect transistor (VeSFET)&#x2014;Design space exploration and DC model","author":"pfitzner","year":"2011","journal-title":"Proc 18th Int Conf MIXDES"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.18"},{"year":"0","key":"ref25"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7091984\/06827975.pdf?arnumber=6827975","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:40:57Z","timestamp":1641987657000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6827975"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5]]},"references-count":37,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2325551","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2015,5]]}}}