{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,25]],"date-time":"2026-10-25T16:42:25Z","timestamp":1792946545663,"version":"4.5.0"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2015,5,1]],"date-time":"2015-05-01T00:00:00Z","timestamp":1430438400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"National Basic Research Program of China (973)","award":["2011CB302503"],"award-info":[{"award-number":["2011CB302503"]}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China (NSFC)","doi-asserted-by":"publisher","award":["61376043"],"award-info":[{"award-number":["61376043"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China (NSFC)","doi-asserted-by":"publisher","award":["61202056"],"award-info":[{"award-number":["61202056"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China (NSFC)","doi-asserted-by":"publisher","award":["61173006"],"award-info":[{"award-number":["61173006"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China (NSFC)","doi-asserted-by":"publisher","award":["61221062"],"award-info":[{"award-number":["61221062"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Strategic Priority Research Program of the Chinese Academy of Sciences","award":["XDA06010401"],"award-info":[{"award-number":["XDA06010401"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,5]]},"DOI":"10.1109\/tvlsi.2014.2325933","type":"journal-article","created":{"date-parts":[[2014,6,19]],"date-time":"2014-06-19T15:22:11Z","timestamp":1403191331000},"page":"879-892","source":"Crossref","is-referenced-by-count":10,"title":["Data Remapping for Static NUCA in Degradable Chip Multiprocessors"],"prefix":"10.1109","volume":"23","author":[{"family":"Ying Wang","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Lei Zhang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Yin-He Han","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Hua-Wei Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Xiaowei Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416644"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/1378533.1378535"},{"key":"ref32","first-page":"544","article-title":"The V-way cache: Demand-based associativity via global replacement","author":"qureshi","year":"2005","journal-title":"Proc 32nd ISCA"},{"key":"ref31","doi-asserted-by":"crossref","first-page":"92","DOI":"10.1145\/1105734.1105747","article-title":"Multifacet’s general execution-driven multiprocessor simulator (GEMS) toolset","volume":"33","author":"martin","year":"2005","journal-title":"ACM SIGARCH Comput Archit News"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090627"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.28"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749758"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2007.81"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749731"},{"key":"ref10","first-page":"603","article-title":"ThermalScope: Multi-scale thermal analysis for nanometer-scale integrated circuits","volume":"28","author":"hassan","year":"2008","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref11","first-page":"70","article-title":"Address remapping for SNUCA in NoC-based degradable chip-multiprocessors","author":"wang","year":"2010","journal-title":"Proc PRDC"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1147\/sj.92.0078"},{"key":"ref13","first-page":"1","article-title":"Achieving fair or differentiated cache sharing in power-constrained chip multiprocessors","author":"wang","year":"2011","journal-title":"Proc 39th ICPP"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/CISIS.2008.97"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.8"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892185"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766701"},{"key":"ref18","first-page":"47","article-title":"SEVA: A soft-error- and variation-aware cache architecture","author":"luong","year":"2006","journal-title":"Proc PRDC"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669127"},{"key":"ref28","author":"pilgrim","year":"2008","journal-title":"Munkres' Assignment Algorithm"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.27"},{"key":"ref3","author":"miller","year":"0","journal-title":"Manufacturing-aware Design Helps Boost IC Yield"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2003.1240944"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837362"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2007.1091"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1151074.1151076"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522348"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2004.1311888"},{"key":"ref9","first-page":"146","article-title":"Modeling and characterizing power variability in multicore architectures","author":"meng","year":"2007","journal-title":"Proc IEEE ISPASS"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.840407"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771785"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555779"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.53"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024928"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.48"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1024393.1024415"},{"key":"ref25","first-page":"423","article-title":"Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches","author":"qureshi","year":"2009","journal-title":"Proc 39th Annu ACM\/IEEE Int Symp Microarchit"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7091984\/06835194.pdf?arnumber=6835194","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:40:56Z","timestamp":1641987656000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6835194"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5]]},"references-count":38,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2325933","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,5]]}}}