{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:43:13Z","timestamp":1761648193177,"version":"3.37.3"},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2015,6,1]],"date-time":"2015-06-01T00:00:00Z","timestamp":1433116800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"CNPQ","award":["472126\/2013-0","302625\/2012-7"],"award-info":[{"award-number":["472126\/2013-0","302625\/2012-7"]}]},{"DOI":"10.13039\/501100002322","name":"CAPES","doi-asserted-by":"crossref","award":["708\/11"],"award-info":[{"award-number":["708\/11"]}],"id":[{"id":"10.13039\/501100002322","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,6]]},"DOI":"10.1109\/tvlsi.2014.2331135","type":"journal-article","created":{"date-parts":[[2014,8,20]],"date-time":"2014-08-20T21:04:48Z","timestamp":1408568688000},"page":"1077-1088","source":"Crossref","is-referenced-by-count":12,"title":["Runtime Adaptive Circuit Switching and Flow Priority in NoC-Based MPSoCs"],"prefix":"10.1109","volume":"23","author":[{"given":"Marcelo","family":"Ruaro","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Everton Alceu","family":"Carara","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6126-6847","authenticated-orcid":false,"given":"Fernando Gehm","family":"Moraes","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.94"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ReCoSoC.2011.5981544"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763073"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.70"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1878961.1878977"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ReCoSoC.2011.5981503"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2012.6271791"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISICir.2011.6131955"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"793","DOI":"10.1109\/71.298203","article-title":"Deadlock-free multicast wormhole routing in 2-D mesh multicomputers","volume":"5","author":"lin","year":"1994","journal-title":"IEEE Trans Parallel Distrib Syst"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2010.5784697"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICM.2011.6177349"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/PDP.2012.20"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"105","DOI":"10.1016\/j.sysarc.2003.07.004","article-title":"QNoC: QoS architecture and design process for network on chip","volume":"50","author":"bolotin","year":"2004","journal-title":"J Syst Archit"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763112"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCPS.2011.6089936"},{"key":"ref7","first-page":"84","article-title":"Design and FPGA implementation of a QoS router for NoC","author":"salah","year":"2011","journal-title":"Proc 3rd Int Conf Next Generation Netw Services (NGNS)"},{"key":"ref2","first-page":"108","article-title":"A 48-core IA-32 message-passing processor with DVFS in 45 nm CMOS","author":"howard","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"journal-title":"Tile-GX Processor Family","year":"2012","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5938113"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.123"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1921249.1921257"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2094215"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7110706\/06849463.pdf?arnumber=6849463","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:06:03Z","timestamp":1642003563000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6849463"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6]]},"references-count":22,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2331135","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2015,6]]}}}