{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:17Z","timestamp":1740133277660,"version":"3.37.3"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2015,6,1]],"date-time":"2015-06-01T00:00:00Z","timestamp":1433116800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2011-TJ-2117"],"award-info":[{"award-number":["2011-TJ-2117"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,6]]},"DOI":"10.1109\/tvlsi.2014.2332469","type":"journal-article","created":{"date-parts":[[2014,7,16]],"date-time":"2014-07-16T18:51:26Z","timestamp":1405536686000},"page":"1050-1062","source":"Crossref","is-referenced-by-count":7,"title":["Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures"],"prefix":"10.1109","volume":"23","author":[{"given":"Wu-Tung","family":"Cheng","sequence":"first","affiliation":[]},{"given":"Yan","family":"Dong","sequence":"additional","affiliation":[]},{"given":"Grady","family":"Gilles","sequence":"additional","affiliation":[]},{"given":"Yu","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Jakub","family":"Janicki","sequence":"additional","affiliation":[]},{"given":"Mark","family":"Kassab","sequence":"additional","affiliation":[]},{"given":"Grzegorz","family":"Mrugalski","sequence":"additional","affiliation":[]},{"given":"Nilanjan","family":"Mukherjee","sequence":"additional","affiliation":[]},{"given":"Janusz","family":"Rajski","sequence":"additional","affiliation":[]},{"given":"Jerzy","family":"Tyszer","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref32","doi-asserted-by":"crossref","first-page":"325","DOI":"10.1109\/VTEST.2003.1197670","article-title":"SOC test scheduling using simulated annealing","author":"zou","year":"2003","journal-title":"Proc 21st VLSI Test Symp (VTS 03)"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364564"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.847893"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.810737"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2003.1252857"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253794"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2205385"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2012.6233003"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2013.6651898"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2203600"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2005.43"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.804382"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.871757"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2021731"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041803"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.844311"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.807895"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ETSYM.2004.1347617"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2004.60"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.169"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.801102"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041747"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.842816"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1023\/A:1014916913577"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/43.875306"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1023\/A:1016589322936"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894302"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2004.1299265"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.826558"},{"journal-title":"Scan Insertion ATPG and Diagnosis—Reference Manual","year":"2014","key":"ref23"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.834228"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176601"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7110706\/06857426.pdf?arnumber=6857426","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:06:03Z","timestamp":1642003563000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6857426"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6]]},"references-count":32,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2332469","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2015,6]]}}}