{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,3,3]],"date-time":"2024-03-03T05:19:17Z","timestamp":1709443157986},"reference-count":23,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2015,6,1]],"date-time":"2015-06-01T00:00:00Z","timestamp":1433116800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,6]]},"DOI":"10.1109\/tvlsi.2014.2333589","type":"journal-article","created":{"date-parts":[[2014,9,15]],"date-time":"2014-09-15T18:42:30Z","timestamp":1410806550000},"page":"1089-1102","source":"Crossref","is-referenced-by-count":3,"title":["An STM-16 Frame Termination VLSI With 2.5-Gb\/s\/Pin Input\/Output Buffers: High-Speed and Low-Power Multi-&lt;inline-formula&gt; &lt;tex-math notation=\"LaTeX\"&gt;$\\mathrm{V}_{\\rm DD}$ &lt;\/tex-math&gt;&lt;\/inline-formula&gt; CMOS\/SIMOX Techniques"],"prefix":"10.1109","volume":"23","author":[{"given":"Nobutaro","family":"Shibata","sequence":"first","affiliation":[]},{"given":"Yusuke","family":"Ohtomo","sequence":"additional","affiliation":[]},{"given":"Mika","family":"Nishisaka","sequence":"additional","affiliation":[]},{"given":"Yasuhiro","family":"Sato","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"661","article-title":"Dynamic floating-body instabilities in partially depleted SOI CMOS circuits","author":"suh","year":"1994","journal-title":"IEEE Int Electron Device Meeting (IEDM) Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VTSA.1999.786054"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1994.383301"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2003.1269160"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2004.1419245"},{"key":"ref15","first-page":"52","article-title":"22 nm high-performance SOI technology featuring dual-embedded stressors, epi-plate high- $k$ deep-trench embedded DRAM and self-aligned via 15LM BEOL","author":"narasimha","year":"2012","journal-title":"IEEE Int Electron Device Meeting (IEDM) Dig Tech Papers"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/4.509865"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/55.585341"},{"key":"ref18","first-page":"79","article-title":"A 0.5-V 1-GHz 32-bit binary-lookahead-carry adder with ED-CMOS\/SOI technology","author":"shibata","year":"2004","journal-title":"IEICE Electron Soc Conf Dig Tech Papers"},{"key":"ref19","first-page":"94","article-title":"Megabit-class size-configurable 250-MHz SRAM macrocells with a squashed memory-cell architecture","author":"shibata","year":"1999","journal-title":"IEICE Trans Electron"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1999.797223"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1049\/el:19780397"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1996.542325"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722310"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/4.661212"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/224081.224086"},{"key":"ref2","first-page":"93","article-title":"Multiplexing of digital signal","author":"yamashita","year":"1998","journal-title":"Easy Digital Transmission"},{"key":"ref1","first-page":"30","article-title":"SDH transmission technology","author":"kasai","year":"1993","journal-title":"SDH Transmission System"},{"key":"ref9","article-title":"An integrated regular and clock generator for dynamic voltage and frequency scaling","author":"burd","year":"1996","journal-title":"Proc IC Design Seminar"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1992.200409"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/16.669534"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/4.257"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/55.511585"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7110706\/06898847.pdf?arnumber=6898847","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:06:03Z","timestamp":1642003563000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6898847"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6]]},"references-count":23,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2333589","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,6]]}}}