{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,10]],"date-time":"2026-01-10T18:43:47Z","timestamp":1768070627491,"version":"3.49.0"},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2015,7,1]],"date-time":"2015-07-01T00:00:00Z","timestamp":1435708800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,7]]},"DOI":"10.1109\/tvlsi.2014.2334351","type":"journal-article","created":{"date-parts":[[2014,7,16]],"date-time":"2014-07-16T18:51:26Z","timestamp":1405536686000},"page":"1350-1354","source":"Crossref","is-referenced-by-count":15,"title":["A High-Performance On-Chip Bus (MSBUS) Design and Verification"],"prefix":"10.1109","volume":"23","author":[{"given":"Xiaokun","family":"Yang","sequence":"first","affiliation":[]},{"given":"Jean H.","family":"Andrian","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000727"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878260"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.200"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2011.0054"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2015665"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1117278.1117293"},{"key":"ref16","first-page":"2002","article-title":"Wire optimization for multimedia SoC and SiP designs","volume":"55","author":"lee","year":"2008","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/bxn059"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2011.79"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2009.01.001"},{"key":"ref4","year":"2001","journal-title":"Open Core Protocol Specification"},{"key":"ref3","year":"2003","journal-title":"Wishbone Bus"},{"key":"ref6","year":"2004","journal-title":"STBus Interconnect"},{"key":"ref5","year":"1999","journal-title":"Coreconnect Bus Architecture"},{"key":"ref8","year":"1999"},{"key":"ref7","first-page":"68","author":"gonzalez","year":"2012","journal-title":"Digital Image Processing"},{"key":"ref2","year":"2003","journal-title":"AMBA AXI Protocol Specification"},{"key":"ref1","year":"1999","journal-title":"AMBA Specification"},{"key":"ref9","year":"2010","journal-title":"MPEG-2 Standards Part1 Systems"},{"key":"ref20","year":"2011","journal-title":"UVM 1 1 Reference Manual"},{"key":"ref21","year":"2012","journal-title":"UVM 1 1 User Guide"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7131599\/06857438.pdf?arnumber=6857438","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:05:11Z","timestamp":1642003511000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6857438"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,7]]},"references-count":21,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2334351","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,7]]}}}