{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,29]],"date-time":"2026-03-29T16:33:36Z","timestamp":1774802016177,"version":"3.50.1"},"reference-count":49,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2015,7,1]],"date-time":"2015-07-01T00:00:00Z","timestamp":1435708800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,7]]},"DOI":"10.1109\/tvlsi.2014.2334635","type":"journal-article","created":{"date-parts":[[2014,8,22]],"date-time":"2014-08-22T19:45:17Z","timestamp":1408736717000},"page":"1254-1267","source":"Crossref","is-referenced-by-count":39,"title":["CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models"],"prefix":"10.1109","volume":"23","author":[{"given":"Norman P.","family":"Jouppi","sequence":"first","affiliation":[]},{"given":"Andrew B.","family":"Kahng","sequence":"additional","affiliation":[]},{"given":"Naveen","family":"Muralimanohar","sequence":"additional","affiliation":[]},{"given":"Vaishnav","family":"Srinivas","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/1555349.1555372"},{"key":"ref38","article-title":"Challenges and solutions for future main memory","year":"2009","journal-title":"Rambus White Paper"},{"key":"ref33","article-title":"Challenges and solutions for GHz DDR3 memory interface design","author":"vaidyanath","year":"2010","journal-title":"Proc Denali MemCon"},{"key":"ref32","article-title":"Overcoming obstacles for closing timing for DDR3–1600 and beyond","author":"ellis","year":"2010","journal-title":"Proc Denali MemCon"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2008.4708764"},{"key":"ref30","author":"taguchi","year":"1996","journal-title":"Introduction to Quality Engineering"},{"key":"ref37","year":"2014"},{"key":"ref36","year":"2014","journal-title":"HP Memory Technology Evolution An Overview of System Memory Technologies"},{"key":"ref35","doi-asserted-by":"crossref","first-page":"100","DOI":"10.1145\/1105734.1105748","article-title":"DRAMsim: A memory system simulator","volume":"33","author":"wang","year":"2005","journal-title":"ACM SIGARCH Comput Archit News"},{"key":"ref34","first-page":"1","article-title":"High performance DDR architecture in Intel Core processors using 32 nm CMOS high-K metal-gate process","author":"mosalikanti","year":"2011","journal-title":"Proc Int Symp IEEE VLSI Design Auto Test"},{"key":"ref28","year":"2014","journal-title":"JEDEC"},{"key":"ref27","year":"2012"},{"key":"ref29","year":"2014","journal-title":"Micron Technical Note"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9781139166980"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429446"},{"key":"ref20","first-page":"156","article-title":"A $47\\times 10$ Gb\/s 1.4 mW\/(Gb\/s) parallel interface in 45 nm CMOS","author":"o\u2019mahony","year":"2010","journal-title":"IEEE Int Solid-State Circuits (ISSCC) Dig Tech Papers"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.16"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"ref24","year":"2010"},{"key":"ref23","year":"2014","journal-title":"Micron DRAM System Power Calculators"},{"key":"ref26","year":"2012"},{"key":"ref25","year":"2009"},{"key":"ref10","year":"2014","journal-title":"1 0 Specifications"},{"key":"ref11","year":"2014","journal-title":"Intel’s Scalable Memory Buffer"},{"key":"ref40","first-page":"496","article-title":"A 1.2 V 12.8 GB\/s 2 Gb mobile wide-I\/O DRAM with $4\\times 128$ I\/Os using TSV-based stacking","author":"kim","year":"2011","journal-title":"IEEE Int Solid-State Circuits (ISSCC) Dig Tech Papers"},{"key":"ref12","first-page":"25","article-title":"BOOM: Enabling mobile memory based low-power server DIMMs","author":"yoon","year":"2012","journal-title":"Proc IEEE Annu Int Symp Comput Arch (ISCA)"},{"key":"ref13","year":"2014","journal-title":"McSim"},{"key":"ref14","year":"2014","journal-title":"J Statist Software"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1109\/ISCA.1995.524546","article-title":"The SPLASH-2 programs: characterization and methodological considerations","author":"woo","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.108"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014199"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908692"},{"key":"ref4","author":"oh","year":"2011","journal-title":"High-Speed Signaling Jitter Modeling Analysis and Budgeting"},{"key":"ref3","author":"bakoglu","year":"1990","journal-title":"Circuits Interconnections and Packaging for VLSI"},{"key":"ref6","article-title":"CACTI-IO","author":"jouppi","year":"2013"},{"key":"ref5","year":"2014","journal-title":"CACTI"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/SLIP.2011.6135437"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337778"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.2007.4387116"},{"key":"ref9","article-title":"Micron reinvents DRAM memory: Hybrid memory cube","author":"baloria","year":"2011","journal-title":"Proc IDF Workshop"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2002.1015043"},{"key":"ref45","year":"2011","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/40.653013"},{"key":"ref47","year":"2011","journal-title":"JEDEC Wide IO Specification JESD229"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/EPEPS.2010.5642561"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.2007.4387151"},{"key":"ref44","year":"0","journal-title":"HP Power Advisor"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7131599\/06882204.pdf?arnumber=6882204","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,7,16]],"date-time":"2023-07-16T05:52:00Z","timestamp":1689486720000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6882204"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,7]]},"references-count":49,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2334635","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,7]]}}}