{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,26]],"date-time":"2026-03-26T19:30:23Z","timestamp":1774553423965,"version":"3.50.1"},"reference-count":8,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2015,7,1]],"date-time":"2015-07-01T00:00:00Z","timestamp":1435708800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Andalusian Government","award":["P09-TIC-5386"],"award-info":[{"award-number":["P09-TIC-5386"]}]},{"name":"Spanish Government, through the European FEDER Program","award":["TEC2011-28302"],"award-info":[{"award-number":["TEC2011-28302"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,7]]},"DOI":"10.1109\/tvlsi.2014.2335233","type":"journal-article","created":{"date-parts":[[2014,7,29]],"date-time":"2014-07-29T18:31:29Z","timestamp":1406658689000},"page":"1345-1349","source":"Crossref","is-referenced-by-count":25,"title":["Background Digital Calibration of Comparator Offsets in Pipeline ADCs"],"prefix":"10.1109","volume":"23","author":[{"given":"Antonio Jose","family":"Gines","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eduardo","family":"Peralias","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Adoracion","family":"Rueda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"1934","article-title":"A simple and accurate method to predict offset voltage in dynamic comparators","author":"he","year":"2008","journal-title":"Proc IEEE Int Symp Circuits Syst (ISCAS)"},{"key":"ref3","first-page":"554","article-title":"A 6 b 0.2-to-0.9 V highly digital flash ADC with comparator redundancy","author":"daly","year":"2008","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2013628"},{"key":"ref5","author":"razavi","year":"2000","journal-title":"Design of Analog CMOS Integrated Circuits"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2010.2051062"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014705"},{"key":"ref2","author":"goes","year":"2001","journal-title":"Systematic design for optimisation of pipelined ADCs"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.121557"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7131599\/06867386.pdf?arnumber=6867386","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:05:11Z","timestamp":1642003511000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6867386"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,7]]},"references-count":8,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2335233","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,7]]}}}