{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,18]],"date-time":"2026-02-18T22:34:46Z","timestamp":1771454086107,"version":"3.50.1"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2015,8,1]],"date-time":"2015-08-01T00:00:00Z","timestamp":1438387200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2015,8,1]],"date-time":"2015-08-01T00:00:00Z","timestamp":1438387200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2015,8,1]],"date-time":"2015-08-01T00:00:00Z","timestamp":1438387200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003051","name":"New Energy and Industrial Technology Development Organization","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003051","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100009105","name":"Ministry of Internal Affairs and Communications","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100009105","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100003382","name":"Core Research for Evolutionary Science and Technology in Japan Science and Technology Agency","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100003382","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Semiconductor Technology Academic Research Center, Tokyo, Japan"},{"name":"Huawei"},{"name":"Berkeley Design Automation for the use of the Analog FastSPICE Platform, Berkeley, CA, USA"},{"name":"VLSI Design and Education Center in collaboration with Cadence Design Systems, Inc., Yokohama, Japan"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,8]]},"DOI":"10.1109\/tvlsi.2014.2340995","type":"journal-article","created":{"date-parts":[[2014,8,11]],"date-time":"2014-08-11T14:20:19Z","timestamp":1407766819000},"page":"1518-1527","source":"Crossref","is-referenced-by-count":12,"title":["Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product"],"prefix":"10.1109","volume":"23","author":[{"given":"James","family":"Lin","sequence":"first","affiliation":[{"name":"Department of Physical Electronics, Tokyo Institute of Technology, Tokyo, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ibuki","family":"Mano","sequence":"additional","affiliation":[{"name":"Department of Physical Electronics, Tokyo Institute of Technology, Tokyo, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masaya","family":"Miyahara","sequence":"additional","affiliation":[{"name":"Department of Physical Electronics, Tokyo Institute of Technology, Tokyo, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Akira","family":"Matsuzawa","sequence":"additional","affiliation":[{"name":"Department of Physical Electronics, Tokyo Institute of Technology, Tokyo, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref32","first-page":"153","article-title":"A 0.6-to-1 V inverter-based 5-bit flash ADC in 90 nm digital CMOS","author":"proesel","year":"2008","journal-title":"Proc IEEE Custom Integr Circuits Conf (CICC)"},{"key":"ref31","first-page":"185","article-title":"A re-configurable 0.5 V to 1.2 V, 10 MS\/s to 100 MS\/s, low-power 10 b $0.13~\\mu$ m CMOS pipeline ADC","author":"kim","year":"2007","journal-title":"Proc IEEE Custom Integr Circuits Conf (CICC)"},{"key":"ref30","first-page":"141","article-title":"A 6 bit, 7 mW, 250 fJ, 700 MS\/s subranging ADC","author":"asada","year":"2009","journal-title":"Proc IEEE Asian Solid-State Circuits Conf (A-SSCC)"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917470"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.891716"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032699"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185352"},{"key":"ref14","first-page":"270","article-title":"A 2.2\/2.7 fJ\/conversion-step 10\/12 b 40 kS\/s SAR ADC with data-driven noise reduction","author":"harpe","year":"2013","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884330"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2191184"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/49.761034"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2010.5716584"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2011.6055410"},{"key":"ref28","first-page":"238","article-title":"An $820~\\mu$ W 9 b 40 MS\/s noise-tolerant dynamic-SAR ADC in 90 nm digital CMOS","author":"giannini","year":"2008","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2006.357848"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2008.4708780"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884801"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON.2011.6157233"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E95.A.456"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2163552"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.856280"},{"key":"ref7","year":"2013","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2012449"},{"key":"ref9","first-page":"93","article-title":"A 0.5-V, 0.05-to-3.2 GHz, 4.1-to-6.4 GHz LC-VCO using E-TSPC frequency divider with forward body bias for sub-picosecond-jitter clock generation","author":"deng","year":"2010","journal-title":"Proc IEEE Asian Solid-State Circuits Conf (A-SSCC)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2218066"},{"key":"ref20","first-page":"26","article-title":"A 6 b 3 GS\/s 11 mW fully dynamic flash ADC in 40 nm CMOS with reduced number of comparators","author":"shu","year":"2012","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2002548"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/EDSSC.2012.6482785"},{"key":"ref24","author":"murmann","year":"2013","journal-title":"ADC Performance Survey 1997-2013"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON.2009.5351489"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/4.400426"},{"key":"ref25","first-page":"334","article-title":"Overview of low-power ULSI circuit techniques","volume":"e78 c","author":"kuroda","year":"1995","journal-title":"IEICE Trans Electron"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7164363\/06875984.pdf?arnumber=6875984","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,18]],"date-time":"2026-02-18T21:26:14Z","timestamp":1771449974000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6875984\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,8]]},"references-count":32,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2340995","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,8]]}}}