{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:07:03Z","timestamp":1761581223410},"reference-count":15,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2015,8,1]],"date-time":"2015-08-01T00:00:00Z","timestamp":1438387200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"University of Alberta China Opportunity Fund"},{"name":"ITC Endowment, Northeastern University, Boston, MA, USA"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,8]]},"DOI":"10.1109\/tvlsi.2014.2341610","type":"journal-article","created":{"date-parts":[[2014,8,11]],"date-time":"2014-08-11T18:20:19Z","timestamp":1407781219000},"page":"1562-1566","source":"Crossref","is-referenced-by-count":23,"title":["A Fault-Tolerant Technique Using Quadded Logic and Quadded Transistors"],"prefix":"10.1109","volume":"23","author":[{"given":"Jie","family":"Han","sequence":"first","affiliation":[]},{"given":"Eugene","family":"Leung","sequence":"additional","affiliation":[]},{"given":"Leibo","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Fabrizio","family":"Lombardi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2008.0133"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785497"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2011.23"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.276"},{"key":"ref14","article-title":"Logic synthesis and optimization benchmarks user guide version 3.0","author":"yang","year":"1991"},{"key":"ref15","article-title":"SIS: A system for sequential circuit synthesis","author":"sentovich","year":"1992"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.97"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1974.224016"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/SBCCI.2000.876036"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICPR.2004.1334455"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2010.2099131"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2007.910870"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2011.1"},{"key":"ref1","year":"2013","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2011.2111460"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7164363\/06875980.pdf?arnumber=6875980","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:42:09Z","timestamp":1642005729000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6875980"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,8]]},"references-count":15,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2341610","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,8]]}}}