{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,3]],"date-time":"2026-05-03T05:43:37Z","timestamp":1777787017726,"version":"3.51.4"},"reference-count":55,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2015,8,1]],"date-time":"2015-08-01T00:00:00Z","timestamp":1438387200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,8]]},"DOI":"10.1109\/tvlsi.2014.2342034","type":"journal-article","created":{"date-parts":[[2014,8,14]],"date-time":"2014-08-14T18:49:53Z","timestamp":1408042193000},"page":"1381-1389","source":"Crossref","is-referenced-by-count":15,"title":["Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits"],"prefix":"10.1109","volume":"23","author":[{"given":"Matthew A.","family":"Morrison","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nagarajan","family":"Ranganathan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jay","family":"Ligatti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","first-page":"17","article-title":"A novel charge recovery logic structure with complementary pass-transistor network","author":"li","year":"2012","journal-title":"Proc Int SoC Design Conf (ISOCC)"},{"key":"ref38","article-title":"Asymptotically zero energy computing using split-level charge recovery logic","author":"younis","year":"1994"},{"key":"ref33","article-title":"Hot-clock nMOS","author":"seitz","year":"1985","journal-title":"Proc Chapel Hill Conf VLSI"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1147\/rd.53.0183"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2011.6144410"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2004.1329406"},{"key":"ref37","first-page":"177","article-title":"Asymptotically zero energy split-level charge recovery logic","author":"younis","year":"1994","journal-title":"Proc Int Workshop Low Power Design"},{"key":"ref36","first-page":"339","article-title":"Optimal design of a reversible full adder","volume":"1","author":"van rentergem","year":"2005","journal-title":"Int J Unconvent Comput"},{"key":"ref35","first-page":"216","article-title":"Common mistakes in adiabatic logic design and how to avoid them","author":"frank","year":"2003","journal-title":"Proc Embedded Syst Appl"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1007\/BF01343193"},{"key":"ref28","year":"2013","journal-title":"PTM 22 nm HSPICE Model"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/81.536746"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.7567\/JJAP.51.06FE10"},{"key":"ref2","first-page":"29","article-title":"The EM side&#x2014;Channel(s)","author":"agrawal","year":"2003","journal-title":"Cryptographic Hardware and Embedded Systems"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VNIS.1995.518887"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2006.342508"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/PHYCMP.1994.363692"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/BF01886518"},{"key":"ref24","article-title":"Asymptotically zero energy computing using split-level charge recovery logic","author":"younis","year":"1994"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/PHYCMP.1992.615546"},{"key":"ref26","first-page":"189","article-title":"A framework for practical low-power digital CMOS systems using adiabatic-switching principles","author":"athas","year":"1994","journal-title":"Proc Int Workshop Low Power Design"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/PHYCMP.1994.363692"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/4.499727"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2247642"},{"key":"ref55","doi-asserted-by":"crossref","first-page":"975","DOI":"10.1109\/TCAD.2014.2313454","article-title":"Synthesis of dual rail adiabatic logic for low power security applications","volume":"33","author":"morrison","year":"2014","journal-title":"IEEE Trans Comput Aided Design"},{"key":"ref54","article-title":"SDMLp&#x2014;Secure differential multiplexer logic: Logic design for DPA resistant cryptographic circuits","author":"ramakrishnan","year":"2012"},{"key":"ref53","year":"0","journal-title":"Internation Organization for Standardization"},{"key":"ref52","author":"rabaey","year":"1996","journal-title":"Digital Integrated Circuits A Design Perspective"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2004.1329406"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIR.2004.1356679"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2006.873382"},{"key":"ref12","year":"0","journal-title":"Internation Organization for Standardization"},{"key":"ref13","first-page":"403","article-title":"A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards","author":"tiri","year":"2002","journal-title":"Proc ESSCIRC"},{"key":"ref14","article-title":"Resistance against implementation attacks: A comparative study of the AES proposals","author":"daemen","year":"1999","journal-title":"Proc Third Advanced Encryption Standard (AES) Candidate Conf"},{"key":"ref15","first-page":"398","article-title":"Towards sound approaches to counteract power-analysis attacks","volume":"1666","author":"chari","year":"1999","journal-title":"Proc 19th Annu Int Cryptol Conf"},{"key":"ref16","first-page":"238","article-title":"Using second-order power analysis to attack DPA resistant software","volume":"1965","author":"messerges","year":"2000","journal-title":"Proc CHES"},{"key":"ref17","first-page":"134","article-title":"Bitslice ciphers and power analysis attacks","author":"daemen","year":"2000","journal-title":"Proc Int Workshop Fast Software Encrypt"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268856"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2007.4402463"},{"key":"ref4","first-page":"252","article-title":"Differential power analysis in the presence of hardware countermeasures","author":"clavier","year":"2000","journal-title":"Cryptographic Hardware and Embedded Systems"},{"key":"ref3","first-page":"104","article-title":"Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems","author":"kocher","year":"1996","journal-title":"Advances in Cryptology"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2012.6224315"},{"key":"ref5","first-page":"388","article-title":"Differential power analysis","volume":"1666","author":"kocher","year":"1999","journal-title":"Advances in Cryptology"},{"key":"ref8","doi-asserted-by":"crossref","DOI":"10.1007\/3-540-10003-2_104","article-title":"Reversible computing","author":"toffoli","year":"1980"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1147\/rd.176.0525"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/ISPACS.2011.6146067"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"219","DOI":"10.1007\/BF01857727","article-title":"Conservative Logic","volume":"21","author":"fredkin","year":"1980","journal-title":"Int J Theoretical Phys"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/DELTA.2002.994673"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.1996.547541"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2004.1329265"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/DELTA.2004.10022"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1049\/el:19970810"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803949"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/4.364447"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2010.77"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7164363\/06878491.pdf?arnumber=6878491","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:42:09Z","timestamp":1642005729000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6878491"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,8]]},"references-count":55,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2342034","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,8]]}}}