{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,9]],"date-time":"2026-05-09T17:07:16Z","timestamp":1778346436759,"version":"3.51.4"},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2015,9,1]],"date-time":"2015-09-01T00:00:00Z","timestamp":1441065600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100004837","name":"Spanish Ministerio de Ciencia e Innovaci\u00f3n","doi-asserted-by":"crossref","award":["TEC2011-27916"],"award-info":[{"award-number":["TEC2011-27916"]}],"id":[{"id":"10.13039\/501100004837","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Universitat Polit\u00e8cnica de Val\u00e8ncia, Gandia, Spain","award":["PAID-06-2012-SP20120625"],"award-info":[{"award-number":["PAID-06-2012-SP20120625"]}]},{"name":"Institut Universitaire de France, Rennes, France"},{"name":"Spanish Ministerio de Educaci\u00f3n","award":["AP2010-5178"],"award-info":[{"award-number":["AP2010-5178"]}]},{"DOI":"10.13039\/501100004795","name":"Institute Universitaire de France","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100004795","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/tvlsi.2014.2344113","type":"journal-article","created":{"date-parts":[[2014,8,21]],"date-time":"2014-08-21T14:28:25Z","timestamp":1408631305000},"page":"1783-1792","source":"Crossref","is-referenced-by-count":43,"title":["Simplified Trellis Min\u2013Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes"],"prefix":"10.1109","volume":"23","author":[{"given":"Jesus O.","family":"Lacruz","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Francisco","family":"Garcia-Herrero","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Declercq","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Javier","family":"Valls","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2008.060527"},{"key":"ref11","article-title":"Décodeurs haute performance et faible complexité pour les codes LDPC binaires et non-binaires","author":"li","year":"2012"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2009.06.070313"},{"key":"ref13","first-page":"831","article-title":"Low latency T-EMS decoder for NB-LDPC codes","author":"li","year":"2013","journal-title":"Proc Asilomar Conf Signals Syst Comput (ASILOMAR)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2046196"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"3430","DOI":"10.1109\/TCSI.2008.924892","article-title":"Algorithms of finding the first two minimum values and their hardware implementation","volume":"55","author":"wey","year":"2008","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2190668"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2013.2256905"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2218839"},{"key":"ref19","author":"rabaey","year":"2003","journal-title":"Digital Integrated Circuits A Design Perspective"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICC.2004.1312606"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ITW.2003.1216697"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISIT.2008.4595129"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2007.894088"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2013.050813.120489"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISWCS.2011.6125307"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4234.681360"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1981.1056404"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2226920"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7217857\/06881677.pdf?arnumber=6881677","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:41:38Z","timestamp":1641987698000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6881677"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":19,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2344113","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,9]]}}}