{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,23]],"date-time":"2026-02-23T23:10:17Z","timestamp":1771888217831,"version":"3.50.1"},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2015,9,1]],"date-time":"2015-09-01T00:00:00Z","timestamp":1441065600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"China National High Technologies Research Program","award":["2012AA012701"],"award-info":[{"award-number":["2012AA012701"]}]},{"name":"State Grid Cooperation of China","award":["SGRI-WD-71-13-014"],"award-info":[{"award-number":["SGRI-WD-71-13-014"]}]},{"name":"Science and Technology Project of Jiangxi Province","award":["20112BBF60050"],"award-info":[{"award-number":["20112BBF60050"]}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61274131"],"award-info":[{"award-number":["61274131"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/tvlsi.2014.2349652","type":"journal-article","created":{"date-parts":[[2014,9,10]],"date-time":"2014-09-10T14:54:22Z","timestamp":1410360862000},"page":"1700-1709","source":"Crossref","is-referenced-by-count":10,"title":["A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels"],"prefix":"10.1109","volume":"23","author":[{"given":"Jianfeng","family":"Zhu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Leibo","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shouyi","family":"Yin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiao","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shaojun","family":"Wei","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2010.5681452"},{"key":"ref11","first-page":"-362i","article-title":"Mapping control intensive kernels onto coarse-grained reconfigurable array architecture","volume":"1","author":"chang","year":"2008","journal-title":"Proc IEEE Int SoC Design Conf (ISOCC)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/223982.225965"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/567067.567085"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/279361.279391"},{"key":"ref15","first-page":"696","article-title":"Clustered VLIW architectures with predicated switching","author":"jacome","year":"2001","journal-title":"Proc 38th Annu Design Autom Conf"},{"key":"ref16","article-title":"The landscape of parallel computing research: A view from Berkeley","author":"asanovic","year":"2006"},{"key":"ref17","year":"2012","journal-title":"Intel Pentium Dual-Core Processor E6000 and E5000 Series Datasheet"},{"key":"ref18","year":"2009","journal-title":"ARM Announces 2GHz Capable Cortex-A9 Intel Pentium Dual-Core Processor Implementation"},{"key":"ref19","first-page":"702","article-title":"High-level synthesis challenges and solutions for a dynamically reconfigurable processor","author":"toi","year":"2006","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.51"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1023\/A:1024499601571"},{"key":"ref6","first-page":"37","article-title":"Understanding sources of ineffciency in general-purpose chips","volume":"10","author":"hameed","year":"2010","journal-title":"Proc 37th Annu ISCA"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/43.833200"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2013.2270465"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2013.6658434"},{"key":"ref2","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-540-45234-8_7","article-title":"ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix","volume":"2778","author":"mei","year":"2003","journal-title":"Field Programmable Logic and Application"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.56"},{"key":"ref9","first-page":"1367","article-title":"State-based full predication for low power coarse-grained reconfigurable architecture","author":"han","year":"2012","journal-title":"Proc Design Automation and Test Eur Conf and Exhibition (DATE)"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485935"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1002\/spe.4380211105"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7217857\/06894174.pdf?arnumber=6894174","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:41:38Z","timestamp":1641987698000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6894174"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":21,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2349652","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,9]]}}}