{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,2]],"date-time":"2026-01-02T07:05:12Z","timestamp":1767337512561},"reference-count":26,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2015,9,1]],"date-time":"2015-09-01T00:00:00Z","timestamp":1441065600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/tvlsi.2014.2350674","type":"journal-article","created":{"date-parts":[[2014,9,15]],"date-time":"2014-09-15T18:42:30Z","timestamp":1410806550000},"page":"1729-1739","source":"Crossref","is-referenced-by-count":25,"title":["A Novel Robust and Low-Leakage SRAM Cell With Nine Carbon Nanotube Transistors"],"prefix":"10.1109","volume":"23","author":[{"given":"Yanan","family":"Sun","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hailong","family":"Jiao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Volkan","family":"Kursun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VDAT.2011.5783611"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.915499"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.907996"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859030"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2167809"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2011.5"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/.2005.1469239"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2009.2025128"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2206781.2206846"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2008.11.062"},{"key":"ref4","first-page":"211","article-title":"Uniform diameter and pitch co-design of 16 nm n-type carbon nanotube channel arrays for VLSI","author":"sun","year":"2011","journal-title":"Proc IEEE 3rd Asia Symp Quality Electron Design"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.4313\/TEEM.2011.12.2.43"},{"key":"ref6","author":"wong","year":"2011","journal-title":"Carbon Nanotube and Graphene Device Physics"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"226","DOI":"10.1109\/VLSISoC.2011.6081642","article-title":"Uniform carbon nanotube diameter and nanoarray pitch for VLSI of 16 nm P-channel MOSFETs","author":"sun","year":"2011","journal-title":"Proc IEEE 19th Int Conf VLSI Syst -Chip (VLSI-SoC)"},{"key":"ref8","first-page":"1452","article-title":"Low power and robust 7T dual-Vt SRAM circuit","author":"tawfik","year":"2008","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref7","first-page":"114","article-title":"Cramming more components onto integrated circuits","volume":"38","author":"moore","year":"1965","journal-title":"Electronics"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2268131"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.917509"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1002\/0470033371"},{"key":"ref20","year":"2014","journal-title":"Stanford CNFET Model—HSPICE"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.18"},{"key":"ref21","year":"2014","journal-title":"MOSIS Scalable CMOS (SCMOS)"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2289411"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2008.2010883"},{"key":"ref26","year":"2014","journal-title":"Clever User’s Manual"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2009.02.006"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7217857\/06898832.pdf?arnumber=6898832","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:41:38Z","timestamp":1642005698000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6898832"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":26,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2350674","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,9]]}}}