{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,1]],"date-time":"2026-08-01T17:43:44Z","timestamp":1785606224648,"version":"3.56.0"},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2015,9,1]],"date-time":"2015-09-01T00:00:00Z","timestamp":1441065600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001868","name":"National Science Council of Taiwan","doi-asserted-by":"crossref","award":["102-2221-E-006-281"],"award-info":[{"award-number":["102-2221-E-006-281"]}],"id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology, Taiwan","doi-asserted-by":"publisher","award":["103-2221-E-006-255"],"award-info":[{"award-number":["103-2221-E-006-255"]}],"id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/tvlsi.2014.2355217","type":"journal-article","created":{"date-parts":[[2014,9,29]],"date-time":"2014-09-29T15:30:21Z","timestamp":1412004621000},"page":"1591-1603","source":"Crossref","is-referenced-by-count":63,"title":["High-Performance Low-Power Carry Speculative Addition With Variable Latency"],"prefix":"10.1109","volume":"23","author":[{"given":"Ing-Chao","family":"Lin","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yi-Ming","family":"Yang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Cheng-Chian","family":"Lin","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228509"},{"key":"ref11","first-page":"1257","article-title":"High performance reliable variable latency carry select addition","author":"du","year":"2012","journal-title":"Proc Design Autom Test Eur Conf Exhibition (DATE)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081446"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/92.924058"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283822"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2026280"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISED.2011.50"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"1874","DOI":"10.1109\/TVLSI.2010.2058874","article-title":"Performance optimization using variable-latency design style","volume":"19","author":"su","year":"2011","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090937"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2010.5450484"},{"key":"ref4","first-page":"957","article-title":"Approximate logic synthesis for error tolerant applications","author":"shin","year":"2010","journal-title":"Proc Design Autom Test Eur Conf Exhibition (DATE)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2217962"},{"key":"ref6","first-page":"69","article-title":"An enhanced low-power high speed adder for error-tolerant application","author":"zhu","year":"2009","journal-title":"Proc Int Symp Intell Control (ISIC)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC.2011.6138614"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/SOCDC.2010.5682905"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"1225","DOI":"10.1109\/TVLSI.2009.2020591","article-title":"Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing","volume":"18","author":"zhu","year":"2010","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993675"},{"key":"ref1","author":"koren","year":"2002","journal-title":"Computer Arithmetic Algorithms"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403679"},{"key":"ref20","author":"rabaey","year":"2003","journal-title":"Digital Integrated Circuits A Design Perspective"},{"key":"ref21","year":"2013","journal-title":"Laker Custom Design and Layout Tool"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7217857\/06913000.pdf?arnumber=6913000","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:41:38Z","timestamp":1641987698000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6913000"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":21,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2355217","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,9]]}}}