{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,25]],"date-time":"2023-09-25T23:55:00Z","timestamp":1695686100160},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2015,9,1]],"date-time":"2015-09-01T00:00:00Z","timestamp":1441065600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/tvlsi.2014.2356432","type":"journal-article","created":{"date-parts":[[2014,10,21]],"date-time":"2014-10-21T18:54:14Z","timestamp":1413917654000},"page":"1879-1888","source":"Crossref","is-referenced-by-count":4,"title":["Analytical Solutions for Distributed Interconnect Models\u2014Part II: Arbitrary Input Response and Multicoupled Lines"],"prefix":"10.1109","volume":"23","author":[{"given":"Amirreza","family":"Baghbanbehrouzian","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nasser","family":"Masoumi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.841065"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000365"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"1068","DOI":"10.1109\/TVLSI.2003.817522","article-title":"Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods","volume":"11","author":"xu","year":"2003","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.800459"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/299996.300020"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1999.777322"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370418"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TADVP.2002.806732"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.857175"},{"key":"ref19","first-page":"20","article-title":"Mémoire sur la méthode générale relative au mouvement de la chaleur dans les corps solides plongés dans des milieux dont la température varie avec le temps","volume":"14","author":"duhamel","year":"0","journal-title":"J École Polytech"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.847895"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/43.664231"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855961"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2009.04.004"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.1004316"},{"key":"ref7","first-page":"1254","article-title":"Analytical crosstalk noise and its induced-delay estimation for distributed RLC interconnects under ramp excitation","author":"kadim","year":"2005","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref2","year":"1977","journal-title":"Semiconductor Industry Association (SIA)"},{"key":"ref1","article-title":"Analytical solutions for distributed interconnect models—Part I: Step input response of finite and semi-infinite lines","author":"behrouzian","year":"2013","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref9","first-page":"334","article-title":"Transmission line design of clock trees","author":"escovar","year":"2002","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design"},{"key":"ref20","author":"kreyszig","year":"2006","journal-title":"Advanced Engineering Mathematics"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923094"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/16.249433"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7217857\/06932430.pdf?arnumber=6932430","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:41:38Z","timestamp":1642005698000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6932430"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":22,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2356432","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,9]]}}}