{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,9]],"date-time":"2026-06-09T16:11:50Z","timestamp":1781021510626,"version":"3.54.1"},"reference-count":20,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2015,10,1]],"date-time":"2015-10-01T00:00:00Z","timestamp":1443657600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100004233","name":"Universitat Polit\u00e8cnica de Val\u00e8ncia, Valencia, Spain, through the DesTT Research Project","doi-asserted-by":"publisher","award":["SP20120806"],"award-info":[{"award-number":["SP20120806"]}],"id":[{"id":"10.13039\/501100004233","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Spanish Ministry of Science and Education","award":["AYA-2009-13300-C03"],"award-info":[{"award-number":["AYA-2009-13300-C03"]}]},{"name":"Arenes Research Project","award":["TIN2012-38308-C02-01"],"award-info":[{"award-number":["TIN2012-38308-C02-01"]}]},{"name":"Research Project entitled Manufacturable and Dependable Multicore Architectures at Nanoscale within the framework of COST ICT Action","award":["1103"],"award-info":[{"award-number":["1103"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,10]]},"DOI":"10.1109\/tvlsi.2014.2357476","type":"journal-article","created":{"date-parts":[[2014,10,2]],"date-time":"2014-10-02T18:47:49Z","timestamp":1412275669000},"page":"2332-2336","source":"Crossref","is-referenced-by-count":58,"title":["MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction"],"prefix":"10.1109","volume":"23","author":[{"given":"Luis-J.","family":"Saiz-Adalid","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Pedro","family":"Reviriego","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Pedro","family":"Gil","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Salvatore","family":"Pontarelli","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Juan Antonio","family":"Maestro","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2009.2015312"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISoC.2011.6081647"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2012.6379048"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2319291"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2008.2005981"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1049\/el.2012.3270"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699220"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2011.2176513"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2007.44"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"178","DOI":"10.1007\/978-3-642-40793-2_17","article-title":"Flexible unequal error control codes with selectable error detection and correction levels","author":"saiz-adalid","year":"2013","journal-title":"Proc Int Conf Comput Safety Rel Security (SAFECOMP)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1147\/rd.282.0124"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2047907"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2010.2042818"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1147\/rd.144.0395"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.40"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/55.843160"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.69"},{"key":"ref1","year":"2014","journal-title":"The International Technology Roadmap for Semiconductors"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2012.2232671"},{"key":"ref20","author":"lin","year":"2004","journal-title":"Error Control Coding"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7274516\/06915762.pdf?arnumber=6915762","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T15:59:25Z","timestamp":1642003165000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6915762"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10]]},"references-count":20,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2357476","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,10]]}}}