{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,17]],"date-time":"2026-09-17T01:41:33Z","timestamp":1789609293177,"version":"build-2803163510"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2015,10,1]],"date-time":"2015-10-01T00:00:00Z","timestamp":1443657600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001868","name":"National Science Council","doi-asserted-by":"publisher","award":["NSC-102-2221-E-006-281"],"award-info":[{"award-number":["NSC-102-2221-E-006-281"]}],"id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology, Taiwan","doi-asserted-by":"publisher","award":["103-2221-E-006-255"],"award-info":[{"award-number":["103-2221-E-006-255"]}],"id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,10]]},"DOI":"10.1109\/tvlsi.2014.2361150","type":"journal-article","created":{"date-parts":[[2014,10,31]],"date-time":"2014-10-31T18:55:42Z","timestamp":1414781742000},"page":"2149-2161","source":"Crossref","is-referenced-by-count":31,"title":["High-Endurance Hybrid Cache Design in CMP Architecture With Cache Partitioning and Access-Aware Policies"],"prefix":"10.1109","volume":"23","author":[{"given":"Ing-Chao","family":"Lin","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jeng-Nian","family":"Chiou","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333717"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2007.1091"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2012.23"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228406"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993611"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228521"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISoC.2011.6081626"},{"key":"ref17","first-page":"1","article-title":"45 nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1 T\/1 MTJ cell","author":"lin","year":"2009","journal-title":"Proc IEEE Int Electron Devices Meeting (IEDM)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2012.6271803"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2483028.2483060"},{"key":"ref28","year":"2013","journal-title":"CACTI An Integrated Cache and Memory Access Time Cycle Time Area Leakage and Dynamic Power Model Version 5 3"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2012.6165071"},{"key":"ref27","first-page":"1","article-title":"Coding last level STT-RAM cache for high endurance and low power","author":"yazdanshenas","year":"2013","journal-title":"Computer Architecture Letters"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993610"},{"key":"ref29","year":"2011","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993609"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref7","first-page":"45","article-title":"Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design","author":"chen","year":"2012","journal-title":"Proc Design Autom Test Eur Conf Exhibition (DATE)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835944"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1088\/0953-8984\/19\/16\/165209"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.43"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835933"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228407"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICPADS.2012.90"},{"key":"ref25","first-page":"737","article-title":"Power and performance of read-write aware hybrid caches with non-volatile memories","author":"wu","year":"2009","journal-title":"Proc Design Autom Test Eur Conf Exhibition (DATE)"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7274516\/06942248.pdf?arnumber=6942248","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T15:59:25Z","timestamp":1642003165000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6942248\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10]]},"references-count":30,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2361150","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,10]]}}}