{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T16:04:01Z","timestamp":1781280241889,"version":"3.54.1"},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2015,10,1]],"date-time":"2015-10-01T00:00:00Z","timestamp":1443657600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,10]]},"DOI":"10.1109\/tvlsi.2014.2361766","type":"journal-article","created":{"date-parts":[[2014,10,21]],"date-time":"2014-10-21T18:54:14Z","timestamp":1413917654000},"page":"2317-2321","source":"Crossref","is-referenced-by-count":36,"title":["A Sub-1-V 65-nm MOS Threshold Monitoring-Based Voltage Reference"],"prefix":"10.1109","volume":"23","author":[{"given":"Xiao Liang","family":"Tan","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Pak Kwong","family":"Chan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Uday","family":"Dasgupta","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672187"},{"key":"ref11","first-page":"332","article-title":"A sub-1V bandgap voltage reference in 32 nm FinFET technology","author":"annema","year":"2009","journal-title":"IEEE Int Solid-State Circuits Conf -Dig Tech Papers (ISSCC)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2206683"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2092997"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.806265"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2008.4708753"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1587\/transele.E93.C.835"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/4.953485"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.905236"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050532"},{"key":"ref3","author":"allen","year":"2000","journal-title":"CMOS Analog Circuits Design"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.899077"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/4.991391"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2021922"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1093\/ietele\/e90-c.10.2044"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609253"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2107583"},{"key":"ref9","first-page":"278","article-title":"A 210 nW 29.3 ppm\/°C 0.7 V voltage reference with a temperature range of -50 to 130 °C in $0.13~\\mu $ m CMOS","author":"lee","year":"2011","journal-title":"Proc IEEE Symp VLSI Circuits"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7274516\/06932441.pdf?arnumber=6932441","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T15:59:25Z","timestamp":1642003165000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6932441\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10]]},"references-count":18,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2361766","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,10]]}}}