{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:22Z","timestamp":1740133282009,"version":"3.37.3"},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2015,12,1]],"date-time":"2015-12-01T00:00:00Z","timestamp":1448928000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation, Durham, NC, USA","doi-asserted-by":"publisher","award":["2233.001"],"award-info":[{"award-number":["2233.001"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,12]]},"DOI":"10.1109\/tvlsi.2014.2385832","type":"journal-article","created":{"date-parts":[[2015,1,12]],"date-time":"2015-01-12T21:15:01Z","timestamp":1421097301000},"page":"3109-3113","source":"Crossref","is-referenced-by-count":1,"title":["Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization"],"prefix":"10.1109","volume":"23","author":[{"given":"Jim","family":"Boley","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peter","family":"Beshay","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Benton","family":"Calhoun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"42","article-title":"Large-scale read\/write margin measurement in 45nm CMOS SRAM arrays","author":"guo","year":"2008","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763081"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609437"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.4304\/jcp.3.5.34-40"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.897148"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908005"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993653"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837310"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2071890"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.364"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457179"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2010.06.009"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052809"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7333028\/07006739.pdf?arnumber=7006739","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:28:05Z","timestamp":1642004885000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7006739\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12]]},"references-count":13,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2385832","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2015,12]]}}}