{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:23Z","timestamp":1740133283746,"version":"3.37.3"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2015,12,1]],"date-time":"2015-12-01T00:00:00Z","timestamp":1448928000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology of Taiwan","doi-asserted-by":"crossref","award":["MOST 103-2221-E-007-125-MY3","MOST 103-2221-E-155-069"],"award-info":[{"award-number":["MOST 103-2221-E-007-125-MY3","MOST 103-2221-E-155-069"]}],"id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100001868","name":"National Science Council of Taiwan","doi-asserted-by":"crossref","award":["102-2221-E-007-140-MY3","NSC 101-2221-E-155-077","NSC 101-2628-E-007-005","NSC 100-2628-E-007-031-MY3","NSC 102-2221-E-155-087"],"award-info":[{"award-number":["102-2221-E-007-140-MY3","NSC 101-2221-E-155-077","NSC 101-2628-E-007-005","NSC 100-2628-E-007-031-MY3","NSC 102-2221-E-155-087"]}],"id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"crossref"}]},{"name":"National Tsing Hua University, Hsinchu, Taiwan","award":["102N2726E1"],"award-info":[{"award-number":["102N2726E1"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015,12]]},"DOI":"10.1109\/tvlsi.2014.2386331","type":"journal-article","created":{"date-parts":[[2015,2,26]],"date-time":"2015-02-26T19:55:01Z","timestamp":1424980501000},"page":"2862-2875","source":"Crossref","is-referenced-by-count":5,"title":["Synthesis for Width Minimization in the Single-Electron Transistor Array"],"prefix":"10.1109","volume":"23","author":[{"given":"Chian-Wei","family":"Liu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chang-En","family":"Chiang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ching-Yi","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yung-Chih","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chun-Yao","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Suman","family":"Datta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vijaykrishnan","family":"Narayanan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"IWLS 2005 Benchmarks","year":"2014","key":"ref32"},{"key":"ref31","first-page":"502","article-title":"Logic synthesis and optimization benchmarks user guide version 3.0","author":"yang","year":"1991"},{"key":"ref30","first-page":"1","article-title":"Rewiring for threshold logic circuit minimization","author":"lin","year":"2014","journal-title":"Proc Design Autom Test Eur Conf Exhibition (DATE)"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1063\/1.1569994"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1063\/1.121014"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/NORCHP.2009.5397816"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1063\/1.2761837"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2000.904388"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131489"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1063\/1.1614845"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1143\/APEX.3.025002"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/16.595938"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2100232"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/S1386-9477(02)00236-9"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1228784.1228813"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/S1386-9477(01)00193-X"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1088\/1742-6596\/38\/1\/026"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105360"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2002.801291"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"76","DOI":"10.1126\/science.1061797","article-title":"Carbon nanotube single-electron transistors at room temperature","volume":"293","author":"postma","year":"2001","journal-title":"Science"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2267453"},{"key":"ref2","first-page":"1","article-title":"Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints","author":"chen","year":"2014","journal-title":"Proc Design Autom Test Eur"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1016\/j.physe.2003.11.080"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.362"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1016\/S0169-4332(03)00089-8"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2008.4585793"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISDRS.2001.984596"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2422094.2422099"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024920"},{"journal-title":"Threshold Logic and Its Applications","year":"1971","author":"muroga","key":"ref26"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1269003"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7333028\/07050261.pdf?arnumber=7050261","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:28:05Z","timestamp":1642004885000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7050261\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12]]},"references-count":32,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2014.2386331","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2015,12]]}}}