{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,11]],"date-time":"2023-09-11T19:11:44Z","timestamp":1694459504572},"reference-count":15,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2016,1,1]],"date-time":"2016-01-01T00:00:00Z","timestamp":1451606400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,1]]},"DOI":"10.1109\/tvlsi.2015.2402392","type":"journal-article","created":{"date-parts":[[2015,3,27]],"date-time":"2015-03-27T17:06:18Z","timestamp":1427475978000},"page":"403-407","source":"Crossref","is-referenced-by-count":4,"title":["Polymorphic Configuration Architecture for CGRAs"],"prefix":"10.1109","volume":"24","author":[{"given":"Syed Mohammad Asad Hassan","family":"Jafri","sequence":"first","affiliation":[]},{"given":"Muhammad Adeel","family":"Tajammul","sequence":"additional","affiliation":[]},{"given":"Ahmed","family":"Hemani","sequence":"additional","affiliation":[]},{"given":"Kolin","family":"Paul","sequence":"additional","affiliation":[]},{"given":"Juha","family":"Plosila","sequence":"additional","affiliation":[]},{"given":"Peeter","family":"Ellervee","sequence":"additional","affiliation":[]},{"given":"Hannu","family":"Tenuhnen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"A dynamically reconfigurable processor architecture","author":"motomura","year":"2002","journal-title":"Microprocessor Forum"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MCSoC.2012.35"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/12.859540"},{"key":"ref13","first-page":"384","article-title":"MuCCRA chips: Configurable dynamically-reconfigurable processors","author":"amano","year":"2007","journal-title":"Proc IEEE Asian Solid-State Circuits Conf (ASSCC)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2011.45"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2013.6523597"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2004.1303113"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VDAT.2005.1500086"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-30117-2_48"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2011.6132719"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2068716.2068722"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2005.1568536"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2228015"},{"key":"ref1","article-title":"Dynamically reconfigurable resource array","author":"shami","year":"2012"},{"key":"ref9","first-page":"47","article-title":"Dynamically programmable gate arrays: A step toward increased computational density","author":"dehon","year":"1996","journal-title":"Proc 4th Canadian Workshop Field-Programmable Devices"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7365521\/07069251.pdf?arnumber=7069251","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T15:57:43Z","timestamp":1642003063000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7069251\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,1]]},"references-count":15,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2402392","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,1]]}}}