{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:25Z","timestamp":1740133285508,"version":"3.37.3"},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2016,2,1]],"date-time":"2016-02-01T00:00:00Z","timestamp":1454284800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology of Taiwan","doi-asserted-by":"crossref","award":["MOST 103-2221-E-110-077-MY3","NSC101-2221-E-110-095-MY2"],"award-info":[{"award-number":["MOST 103-2221-E-110-077-MY3","NSC101-2221-E-110-095-MY2"]}],"id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,2]]},"DOI":"10.1109\/tvlsi.2015.2410218","type":"journal-article","created":{"date-parts":[[2015,3,20]],"date-time":"2015-03-20T15:23:02Z","timestamp":1426864982000},"page":"784-788","source":"Crossref","is-referenced-by-count":1,"title":["A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies"],"prefix":"10.1109","volume":"24","author":[{"given":"Tong-Yu","family":"Hsieh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chih-Hao","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tsung-Liang","family":"Chih","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ya-Hsiu","family":"Chi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"journal-title":"SPEC’s Benchmarks","year":"2015","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2010.20"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.840407"},{"journal-title":"Computer Organization and Design The Hardware\/Software Interface","year":"2013","author":"patterson","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2009.5413171"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669127"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2007.81"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"742","DOI":"10.1109\/TVLSI.2005.848824","article-title":"A built-in self-repair design for RAMs with 2-D redundancy","volume":"13","author":"li","year":"2005","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"journal-title":"System-on-Chip Test Architectures Nanometer Design for Testability","year":"2008","author":"wang","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2001.990303"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355594"},{"key":"ref9","first-page":"81","article-title":"An integrated ECC and redundancy repair scheme for memory reliability enhancement","author":"su","year":"2005","journal-title":"Proc 20th IEEE Int Symp Defect Fault Tolerance VLSI Syst (DFT)"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7386794\/7064734.pdf?arnumber=7064734","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:47:21Z","timestamp":1641988041000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7064734\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,2]]},"references-count":13,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2410218","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2016,2]]}}}