{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,2]],"date-time":"2026-03-02T10:57:56Z","timestamp":1772449076885,"version":"3.50.1"},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2016,2,1]],"date-time":"2016-02-01T00:00:00Z","timestamp":1454284800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003836","name":"IC Design Education Center","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003836","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003725","name":"Basic Science Research Program through the National Research Foundation of Korea within the Ministry of Science, ICT and Future Planning","doi-asserted-by":"publisher","award":["NRF-2014R1A2A1A05004316"],"award-info":[{"award-number":["NRF-2014R1A2A1A05004316"]}],"id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,2]]},"DOI":"10.1109\/tvlsi.2015.2418579","type":"journal-article","created":{"date-parts":[[2015,4,14]],"date-time":"2015-04-14T14:40:52Z","timestamp":1429022452000},"page":"789-793","source":"Crossref","is-referenced-by-count":37,"title":["A 21-Gbit\/s 1.63-pJ\/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method"],"prefix":"10.1109","volume":"24","author":[{"given":"Yong-Hun","family":"Kim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Young-Ju","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Taeho","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lee-Sup","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2136590"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884342"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014733"},{"key":"ref13","first-page":"30","article-title":"A 66 Gb\/s 46 mW 3-tap decision-feedback equalizer in 65 nm CMOS","author":"lu","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/4.661206"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2216414"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2040116"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2131730"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2022917"},{"key":"ref19","first-page":"216","article-title":"A 19 Gb\/s 38 mW 1-tap speculative DFE receiver in 90 nm CMOS","author":"turker","year":"2009","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185342"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2196313"},{"key":"ref6","first-page":"206","article-title":"A 20-Gb\/s, 0.66-pJ\/bit serial receiver with 2-stage continuous-time linear equalizer and 1-tap decision feedback equalizer in 45 nm SOI CMOS","author":"proesel","year":"2011","journal-title":"Proc Symp VLSI Circuits (VLSIC)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2134450"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.845562"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.880629"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2168871"},{"key":"ref1","first-page":"350","article-title":"Analog-DFE-based 16 Gb\/s SerDes in 40 nm CMOS that operates across 34 dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver","author":"joy","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892166"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.903076"},{"key":"ref22","first-page":"444","article-title":"A 20 Gb\/s digitally adaptive equalizer\/DFE with blind sampling","author":"ying","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"},{"key":"ref21","first-page":"42","article-title":"A 0.94 mW\/Gb\/s 22 Gb\/s 2-tap partial-response DFE receiver in 40 nm LP CMOS","author":"jung","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7386794\/7086055.pdf?arnumber=7086055","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:47:21Z","timestamp":1641988041000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7086055\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,2]]},"references-count":22,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2418579","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,2]]}}}