{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,18]],"date-time":"2025-12-18T14:01:17Z","timestamp":1766066477389,"version":"3.37.3"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2016,2,1]],"date-time":"2016-02-01T00:00:00Z","timestamp":1454284800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"National Research Foundation of Korea within the Ministry of Education, Science and Technology through Korean Government","award":["2012R1A2A2A06047297"],"award-info":[{"award-number":["2012R1A2A2A06047297"]}]},{"name":"IT Research and Development Program within the Ministry of Knowledge Economy through the Korea Evaluation Institute of Industrial Technology","award":["10041608"],"award-info":[{"award-number":["10041608"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,2]]},"DOI":"10.1109\/tvlsi.2015.2420315","type":"journal-article","created":{"date-parts":[[2015,4,23]],"date-time":"2015-04-23T16:30:02Z","timestamp":1429806602000},"page":"453-464","source":"Crossref","is-referenced-by-count":12,"title":["Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching"],"prefix":"10.1109","volume":"24","author":[{"given":"Junwhan","family":"Ahn","sequence":"first","affiliation":[]},{"given":"Sungjoo","family":"Yoo","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6138-6697","authenticated-orcid":false,"given":"Kiyoung","family":"Choi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref32","first-page":"289","article-title":"Meeting midway: Improving CMP performance with memory-side prefetching","author":"yedlapalli","year":"2013","journal-title":"Proc Int Conf Parallel Arch Compil Tech"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003576"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488874"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"ref11","first-page":"33","article-title":"CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory","author":"chen","year":"2012","journal-title":"Proc Design Autom Test Eur"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"ref14","first-page":"145","article-title":"Memory-centric system interconnect design with hybrid memory cubes","author":"kim","year":"2013","journal-title":"Proc Int Conf Parallel Arch Compil Tech"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908692"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2075410"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1186736.1186737","article-title":"SPEC CPU2006 benchmark descriptions","volume":"34","author":"henning","year":"2006","journal-title":"ACM SIGARCH Comput Archit News"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.28"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379244"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2002.10"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593128"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.86"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346185"},{"year":"2013","key":"ref6","article-title":"Hybrid memory cube specification 1.0"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669151"},{"journal-title":"High-Speed Serial I\/O Made Simple","year":"2005","author":"athavale","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669154"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379259"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242474"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1990.134547"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.349"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.32"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.44"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657041"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2004.1347970"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/CONECT.2003.1231472"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7386794\/7093180.pdf?arnumber=7093180","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:47:21Z","timestamp":1641988041000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7093180\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,2]]},"references-count":32,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2420315","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2016,2]]}}}