{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T10:46:20Z","timestamp":1761561980050},"reference-count":43,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2016,3,1]],"date-time":"2016-03-01T00:00:00Z","timestamp":1456790400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"German Research Foundation within the National Focal Program through the Dependable Embedded Systems"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,3]]},"DOI":"10.1109\/tvlsi.2015.2425653","type":"journal-article","created":{"date-parts":[[2015,5,8]],"date-time":"2015-05-08T18:57:44Z","timestamp":1431111464000},"page":"932-943","source":"Crossref","is-referenced-by-count":39,"title":["Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames"],"prefix":"10.1109","volume":"24","author":[{"given":"Mojtaba","family":"Ebrahimi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Parthasarathy Murali B.","family":"Rao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Razi","family":"Seyyedi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mehdi B.","family":"Tahoori","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2009.30"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2011.5993833"},{"key":"ref33","article-title":"Protecting caches against multiple bit upsets using embedded erasure coding","author":"banaiyanmofrad","year":"2014","journal-title":"Proc Eur Test Symp (ETS)"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2004.1311882"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/263876.263881"},{"key":"ref30","first-page":"1","article-title":"Erasure codes for storage applications","author":"plank","year":"2005","journal-title":"Proc 4th Usenix Conf File Storage Technol"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2014.043"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2009.2015312"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/762476.762480"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.19"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2671181"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1994.315642"},{"key":"ref11","article-title":"Triple module redundancy design techniques for Virtex FPGAs","author":"carmichael","year":"2001"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.16"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2008.2000852"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2213102"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382552"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364504"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2008.2001422"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2013.6548910"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2011.6132703"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-013-5385-9"},{"key":"ref4","first-page":"1","article-title":"Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency","author":"dorsey","year":"2010"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2014.6881539"},{"key":"ref3","first-page":"1","article-title":"NSEU mitigation in avionics applications","author":"hu","year":"2011"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2012.2218128"},{"key":"ref29","year":"2015","journal-title":"JEDEC Standard"},{"key":"ref5","article-title":"Meeting the performance and power imperative of the zettabyte era with generation 10","year":"0"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2047907"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488858"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228572"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2005.860675"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2011.5784522"},{"key":"ref20","first-page":"144","article-title":"Fast local scrubbing for field-programmable gate array’s configuration memory","volume":"10","author":"vera","year":"2013","journal-title":"J Aerosp Inf Syst"},{"key":"ref22","article-title":"Enhancing robust SEU mitigation with 28-nm FPGAs","year":"2010"},{"key":"ref21","article-title":"Single event upset (SEU) detection and correction using Virtex-4 devices","author":"jones","year":"2007"},{"key":"ref42","article-title":"Virtex-6 FPGA configuration user guide","year":"2013","journal-title":"Xilinx Corporation"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISIE.2010.5637493"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763277"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2095435"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1002\/0470035706"},{"key":"ref43","article-title":"SEU strategies for Virtex-5 devices","author":"chapman","year":"2010"},{"key":"ref25","article-title":"LogiCORE IP soft error mitigation controller v3.4","year":"2012"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7416268\/7104165.pdf?arnumber=7104165","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:48:35Z","timestamp":1642006115000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7104165\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,3]]},"references-count":43,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2425653","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,3]]}}}