{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,29]],"date-time":"2026-03-29T02:27:35Z","timestamp":1774751255076,"version":"3.50.1"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2016,3,1]],"date-time":"2016-03-01T00:00:00Z","timestamp":1456790400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"ICT Research and Development Program through the Ministry of Science, ICT and Future Planning\/Institute for Information and Communications Technology Promotion","award":["10041313"],"award-info":[{"award-number":["10041313"]}]},{"name":"National Research Foundation through the Korean Government","award":["2010-0029366"],"award-info":[{"award-number":["2010-0029366"]}]},{"name":"National Research Foundation through the Korean Government","award":["2014R1A2A2A01007051"],"award-info":[{"award-number":["2014R1A2A2A01007051"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,3]]},"DOI":"10.1109\/tvlsi.2015.2429587","type":"journal-article","created":{"date-parts":[[2015,5,25]],"date-time":"2015-05-25T18:33:11Z","timestamp":1432578791000},"page":"871-883","source":"Crossref","is-referenced-by-count":6,"title":["Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems"],"prefix":"10.1109","volume":"24","author":[{"given":"Jongmin","family":"Lee","sequence":"first","affiliation":[]},{"given":"Soontae","family":"Kim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/800015.808204"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/2.55497"},{"key":"ref31","author":"culler","year":"1997","journal-title":"Parallel Computer Architecture A Hardware\/Software Approach"},{"key":"ref30","first-page":"11","article-title":"Mitigating multi-bit soft errors in L1 caches using last-store prediction","author":"gold","year":"2007","journal-title":"Proc Int Workshop Archit Support Gigascale Integr"},{"key":"ref10","first-page":"1","article-title":"CACTI 6.0: A tool to model large caches","author":"muralimanohar","year":"2009","journal-title":"Proc Int Symp Microarchitecture"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645809"},{"key":"ref12","first-page":"68","article-title":"Design of a predictive filter cache for energy savings in high performance processor architectures","author":"tang","year":"2001","journal-title":"Proc Int Conf Comput Design VLSI Comput Processors (ICCD)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313856"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2349503"},{"key":"ref15","first-page":"328","article-title":"A compiler-in-the-loop framework to explore horizontally partitioned cache architectures","author":"shrivastava","year":"2008","journal-title":"Proc Asia South Pacific Design Autom Conf (ASPDAC)"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313948"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997880"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2001.953287"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.45"},{"key":"ref4","year":"0","journal-title":"ARM Cortex A9"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2005.23"},{"key":"ref3","year":"0","journal-title":"Intel XScale Microarchitecture"},{"key":"ref27","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref6","author":"hennessy","year":"2011","journal-title":"Computer Architecture A Quantitative Approach"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253181"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1997.569650"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1210268.1210272"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1994.331913"},{"key":"ref2","year":"0","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref1","first-page":"1","article-title":"Race to exascale: Opportunities and challenges","author":"sodani","year":"2011","journal-title":"Proc MICRO Keynote Talk"},{"key":"ref9","first-page":"3","article-title":"MiBench: A free, commercially representative embedded benchmark suite","author":"guthaus","year":"2001","journal-title":"Proc IEEE Int Workshop Workload Characterization (WWC)"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594318"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183548"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/514216.514219"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1993.698560"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2000.898055"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1994.717450"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7416268\/7112510.pdf?arnumber=7112510","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:48:36Z","timestamp":1642006116000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7112510\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,3]]},"references-count":33,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2429587","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,3]]}}}