{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,10]],"date-time":"2025-12-10T15:22:06Z","timestamp":1765380126607},"reference-count":52,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2016,3,1]],"date-time":"2016-03-01T00:00:00Z","timestamp":1456790400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,3]]},"DOI":"10.1109\/tvlsi.2015.2440392","type":"journal-article","created":{"date-parts":[[2015,6,23]],"date-time":"2015-06-23T18:53:21Z","timestamp":1435085601000},"page":"1003-1014","source":"Crossref","is-referenced-by-count":44,"title":["Modeling and Optimization of Memristor and STT-RAM-Based Memory for Low-Power Applications"],"prefix":"10.1109","volume":"24","author":[{"given":"Yasmin","family":"Halawani","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Baker","family":"Mohammad","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dirar","family":"Homouz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mahmoud","family":"Al-Qutayri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hani","family":"Saleh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1063\/1.3429250"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2169962"},{"key":"ref33","article-title":"Energy-performance characterization of CMOS\/magnetic tunnel junction (MTJ) hybrid logic circuits","author":"ren","year":"2011"},{"key":"ref32","doi-asserted-by":"crossref","first-page":"130","DOI":"10.1109\/DTIS.2009.4938040","article-title":"Dynamic compact model of spin-transfer torque based magnetic tunnel junction (MTJ)","author":"faber","year":"2009","journal-title":"Proc 4th IEEE Int Conf Design Technol Integr Syst Nanoscale Era (DTIS)"},{"key":"ref31","year":"2014"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1063\/1.4726421"},{"key":"ref37","article-title":"Modeling spintronics devices in Verilog-A for use with industry-standard simulation tools","author":"engelbrecht","year":"2011"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2267754"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2178416"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/BMAS.2006.283467"},{"key":"ref28","doi-asserted-by":"crossref","first-page":"429","DOI":"10.1038\/nnano.2008.160","article-title":"Memristive switching mechanism for metal\/oxide\/metal nanodevices","volume":"3","author":"yang","year":"2008","journal-title":"Nature Nanotechnol"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2158004"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/s00339-008-4975-3"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1614379.1614385"},{"key":"ref1","article-title":"How to design nanowatt microsystem","author":"sylvester","year":"0"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/22\/50\/505402"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1038\/453042a"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1038\/nature06932"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2013.6571821"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2227519"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1088\/0143-0807\/30\/4\/001"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1002\/smll.200801323"},{"key":"ref50","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4614-8881-1","author":"mohammad","year":"2014","journal-title":"Embedded Memory Design for Multi-Core and Systems on Chip"},{"key":"ref51","article-title":"Memristors&#x2014;Not just memory","author":"kvatinsky","year":"0"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.5772\/663"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.821776"},{"key":"ref11","year":"2011","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref40","article-title":"SPICE modeling of STT-RAM for resilient design","author":"xu","year":"2012","journal-title":"Proc 5th Int MOS-AK\/GSA Workshop"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2010.2075920"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2049867"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1063\/1.3640806"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC.2013.6818813"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2011.2158796"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-34428-2_9"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2012.240"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2013.6815515"},{"key":"ref4","first-page":"1110","article-title":"Memory wall","author":"mckee","year":"2011","journal-title":"Encyclopedia of Parallel Computing"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-40009-4_21"},{"key":"ref6","article-title":"Embedded memory test and repair optimizes SoC yields","author":"kaushik","year":"2012"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-88497-4_2"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2008.4708784"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.115"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/VARI.2014.6957074"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2011.6044889"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/ICSENS.2009.5398442"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749716"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2388587"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2013.6651928"},{"key":"ref42","first-page":"36","article-title":"Behavioural model of spin torque transfer magnetic tunnel junction, using Verilog-A","volume":"1","author":"garg","year":"2012","journal-title":"Int J Adv Res Technol"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2275082"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228406"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2012.6213651"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7416268\/7131587.pdf?arnumber=7131587","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:48:36Z","timestamp":1642006116000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7131587\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,3]]},"references-count":52,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2440392","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,3]]}}}