{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:34:18Z","timestamp":1773246858001,"version":"3.50.1"},"reference-count":44,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Hong Kong University of Science and Technology, Hong Kong"},{"name":"Research Project","award":["GRF620911"],"award-info":[{"award-number":["GRF620911"]}]},{"name":"Research Project","award":["GRF620512"],"award-info":[{"award-number":["GRF620512"]}]},{"name":"Research Project","award":["DAG11EG05S"],"award-info":[{"award-number":["DAG11EG05S"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/tvlsi.2015.2445825","type":"journal-article","created":{"date-parts":[[2015,7,10]],"date-time":"2015-07-10T18:46:55Z","timestamp":1436554015000},"page":"1574-1587","source":"Crossref","is-referenced-by-count":14,"title":["Improve Chip Pin Performance Using Optical Interconnects"],"prefix":"10.1109","volume":"24","author":[{"given":"Zhehui","family":"Wang","sequence":"first","affiliation":[]},{"given":"Jiang","family":"Xu","sequence":"additional","affiliation":[]},{"given":"Peng","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Xuan","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Zhe","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Luan Huu Kinh","family":"Duong","sequence":"additional","affiliation":[]},{"given":"Zhifei","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Rafael Kioji Vivas","family":"Maeda","sequence":"additional","affiliation":[]},{"given":"Haoran","family":"Li","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","article-title":"Multilayer PCB stackup planning","author":"olney","year":"2011"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/JLT.2013.2279791"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSTQE.2010.2048306"},{"key":"ref32","first-page":"1","article-title":"1.55 $\\mu $ m InP-based VCSEL with enhanced modulation bandwidths » 10 GHz up to 85 °C","author":"hofmann","year":"2009","journal-title":"Proc OFC"},{"key":"ref31","year":"2001","journal-title":"Accurately estimating optical receiver sensitivity"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9781139166980"},{"key":"ref37","author":"brillouin","year":"1960","journal-title":"Wave Propagation and Group Velocity"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2006.877061"},{"key":"ref35","year":"2013","journal-title":"RO4000 Series High Frequency Circuit Materials"},{"key":"ref34","year":"2014","journal-title":"Designing with high-density BGA packages for Altera devices"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/50.737423"},{"key":"ref40","article-title":"ATE interconnect performance to 43 Gbps using advanced PCB materials","author":"barnes","year":"2008"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/SPI.2002.258274"},{"key":"ref12","first-page":"1067","article-title":"Comparison of electrical and optical interconnect","author":"shin","year":"2003","journal-title":"Proc 53rd Electron Compon Technol Conf"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"791","DOI":"10.1109\/ASPDAC.2015.7059107","article-title":"Alleviate chip I\/O pin constraints for multicore processors through optical interconnects","author":"wang","year":"2015","journal-title":"Asia South Pacific Design Autom Conf (ASP-DAC)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/33.56155"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2014884"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2014298"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2020331"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.833663"},{"key":"ref28","author":"thierauf","year":"2004","journal-title":"High-Speed Circuit Board Signal Integrity"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JLT.2010.2101580"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1002\/lpor.201100017"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TADVP.2009.2014877"},{"key":"ref6","first-page":"116","article-title":"Power comparison between high-speed electrical and optical interconnects for inter-chip communication","author":"cho","year":"2004","journal-title":"Proc IEEE Int Interconnect Technol Conf"},{"key":"ref29","year":"2000","journal-title":"Performance Characteristics of IC Packages"},{"key":"ref5","year":"2015","journal-title":"Optical and Electrical Interfaces and Links (OEIL)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1364\/AO.27.001742"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2006.10.001"},{"key":"ref2","article-title":"Crosstalk coupling: Single-ended vs. differential","author":"brooks","year":"2005"},{"key":"ref1","year":"2011","journal-title":"PCI Express 4 0 Evolution to 16GT\/s Twice the Throughput of PCI Express 3 0 Technology"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1364\/JOCN.2.000206"},{"key":"ref20","year":"2005","journal-title":"Flip Chip Ball Grid Array Package Reference Guide"},{"key":"ref22","year":"2007","journal-title":"Single-Mode Fiber Optics"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1143\/JJAP.45.6071"},{"key":"ref42","first-page":"1","article-title":"High-speed serial differential signaling links with commercial equalizer","author":"\u0161ev?\u00edk","year":"2010","journal-title":"Proc 20th Int Conf Radioelektronika"},{"key":"ref24","year":"2013","journal-title":"Saturn PCB Design Toolkit"},{"key":"ref41","year":"2010","journal-title":"Modeling and design considerations for 10 Gbps connectors"},{"key":"ref23","author":"bogatin","year":"2009","journal-title":"Signal and Power Integrity"},{"key":"ref44","year":"2015","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1038\/nature03569"},{"key":"ref43","year":"2011","journal-title":"High-speed PCB Design Considerations"},{"key":"ref25","first-page":"17","article-title":"Design specifications—A review of IPC-2152, current carrying capacity for printed board design","volume":"26","author":"jouppi","year":"2009","journal-title":"Printed circuit design & fab"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7436835\/7154512.pdf?arnumber=7154512","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T02:34:43Z","timestamp":1633919683000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7154512\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":44,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2445825","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,4]]}}}