{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,5]],"date-time":"2026-01-05T11:08:09Z","timestamp":1767611289004,"version":"3.37.3"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology, Taiwan","doi-asserted-by":"publisher","award":["MOST 103-2220-E-007-023","MOST 103-2221-E-007-135-MY3","MOST 104-2220-E-007-008"],"award-info":[{"award-number":["MOST 103-2220-E-007-023","MOST 103-2221-E-007-135-MY3","MOST 104-2220-E-007-008"]}],"id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/tvlsi.2015.2448575","type":"journal-article","created":{"date-parts":[[2015,7,17]],"date-time":"2015-07-17T18:52:06Z","timestamp":1437159126000},"page":"1441-1449","source":"Crossref","is-referenced-by-count":20,"title":["A 0.5 V 1.28-MS\/s 4.68-fJ\/Conversion-Step SAR ADC With Energy-Efficient DAC and Trilevel Switching Scheme"],"prefix":"10.1109","volume":"24","author":[{"given":"Kuan-Ting","family":"Lin","sequence":"first","affiliation":[]},{"given":"Yu-Wei","family":"Cheng","sequence":"additional","affiliation":[]},{"given":"Kea-Tiong","family":"Tang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2048498"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2012.6271770"},{"key":"ref12","first-page":"2239","article-title":"A 0.6 V 8 b 100 MS\/s SAR ADC with minimized DAC capacitance and switching energy in 65 nm CMOS","author":"wu","year":"2013","journal-title":"Proc IEEE ISCAS"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.906210"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1049\/el:19990028"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/4.760369"},{"key":"ref16","first-page":"247","author":"laker","year":"1994","journal-title":"Design of Analog Integrated Circuits and Systems"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2012.6271767"},{"key":"ref18","first-page":"392","article-title":"A voltage-controlled capacitance offset calibration technique for high resolution dynamic comparator","author":"chan","year":"2009","journal-title":"Proc IEEE Int SoC Design Conf"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2143870"},{"key":"ref4","first-page":"1","article-title":"A 0.5 V 1 KS\/s 2.5 nW 8.52-ENOB 6.8 fJ\/conversion-step SAR ADC for biomedical applications","author":"lu","year":"2011","journal-title":"Proc IEEE CICC"},{"key":"ref3","first-page":"339","article-title":"A 0.5 V 20 fJ\/conversionstep rail-to-rail SAR ADC with programmable time-delayed control units for low-power biomedical application","author":"chang","year":"2011","journal-title":"Proc IEEE ESSCIRC"},{"key":"ref6","first-page":"236","article-title":"Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters","author":"lee","year":"2008","journal-title":"Proc IEEE ISCAS"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892169"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2190117"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042254"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185352"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.933473"},{"key":"ref1","first-page":"92","article-title":"A 3.2 fJ\/c.-s. 0.35 V 10 b 100 KS\/s SAR ADC in 90 nm CMOS","author":"tai","year":"2012","journal-title":"IEEE Symp VLSI Circuits Dig"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2191209"},{"journal-title":"An Introduction to Mixed-Signal IC Test and Measurement","year":"2011","author":"burns","key":"ref22"},{"key":"ref21","first-page":"2243","article-title":"A SAR ADC with energy-efficient DAC and tri-level switching scheme","author":"lin","year":"2013","journal-title":"Proc IEEE ISCAS"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2254551"},{"key":"ref23","first-page":"270","article-title":"A 2.2\/2.7 fJ\/conversion-step 10\/12 b 40 kS\/s SAR ADC with data-driven noise reduction","author":"harpe","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"},{"key":"ref25","first-page":"381","article-title":"An 8 bit 0.35–0.8 V 0.5–30 MS\/s 2 bit\/step SAR ADC with wide range threshold configuring comparator","author":"yoshioka","year":"2012","journal-title":"Proc Eur Solid-State Circuits Conf (ESSCIRC)"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7436835\/7161385.pdf?arnumber=7161385","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T02:34:44Z","timestamp":1633919684000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7161385\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":25,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2448575","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2016,4]]}}}