{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T17:01:05Z","timestamp":1774630865131,"version":"3.50.1"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/tvlsi.2015.2451658","type":"journal-article","created":{"date-parts":[[2015,9,18]],"date-time":"2015-09-18T06:09:18Z","timestamp":1442556558000},"page":"1280-1292","source":"Crossref","is-referenced-by-count":12,"title":["Hybrid LUT\/Multiplexer FPGA Logic Architectures"],"prefix":"10.1109","volume":"24","author":[{"given":"Stephen Alexander","family":"Chin","sequence":"first","affiliation":[]},{"given":"Jason","family":"Luu","sequence":"additional","affiliation":[]},{"given":"Safeen","family":"Huda","sequence":"additional","affiliation":[]},{"given":"Jason H.","family":"Anderson","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"188","article-title":"Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates","author":"hu","year":"2007","journal-title":"Proc IEEE ICCAD"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/127601.127673"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2006.229287"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-63465-7_226"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718328"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2013.19"},{"key":"ref17","year":"2011","journal-title":"Virtex5 FPGA User Guide"},{"key":"ref18","year":"2011","journal-title":"Stratix IV Device Handbook"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/360276.360299"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950423"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145715"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/4.62145"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722215"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272537"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjjip.17.242"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145708"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1044111.1044113"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718327"},{"key":"ref22","year":"2014"},{"key":"ref21","year":"2015","journal-title":"Predictive Technology Model"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/503048.503071"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397290"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7436835\/7271109.pdf?arnumber=7271109","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T02:34:44Z","timestamp":1633919684000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7271109\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":24,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2451658","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,4]]}}}