{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:27Z","timestamp":1740133287451,"version":"3.37.3"},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61402060"],"award-info":[{"award-number":["61402060"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"National 863 Programs","award":["2013AA013202","2015AA015304"],"award-info":[{"award-number":["2013AA013202","2015AA015304"]}]},{"name":"Chongqing High-Tech Research Program","award":["cstc2014yykfB40007"],"award-info":[{"award-number":["cstc2014yykfB40007"]}]},{"name":"Hong Kong Special Administrative Region","award":["R9336"],"award-info":[{"award-number":["R9336"]}]},{"name":"Public Sector Research Funding through the Agency for Science, Technology and Research, Singapore"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/tvlsi.2015.2452910","type":"journal-article","created":{"date-parts":[[2015,8,14]],"date-time":"2015-08-14T20:33:07Z","timestamp":1439584387000},"page":"1546-1559","source":"Crossref","is-referenced-by-count":10,"title":["Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip"],"prefix":"10.1109","volume":"24","author":[{"given":"Weichen","family":"Liu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xuan","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jiang","family":"Xu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"JEDEC Standard JESD89","year":"2001","key":"ref33"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2005.69"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2240697"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1147\/rd.523.0285"},{"journal-title":"Synopsys Design Compiler","year":"2013","key":"ref35"},{"journal-title":"Nangate 45nm open cell library","year":"2013","key":"ref34"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090752"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024755"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457042"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2013.103"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1151074.1151076"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2013.6670342"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/NORCHP.2006.329272"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2012.6398330"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2007.90"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2009.5270340"},{"journal-title":"SystemC","year":"2013","key":"ref28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297681"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.91"},{"journal-title":"Fault-Tolerant Computer System Design","year":"1996","author":"pradhan","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146926"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2011.49"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364501"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/71.584093"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.42"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2011.48"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2005.34"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.855790"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICASID.2012.6325306"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICPADS.2008.18"},{"journal-title":"On-chip interconnection networks Why they are different and how to compare them","year":"2006","author":"zafar","key":"ref21"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1999946.1999967"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243952"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2007.4402516"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2162348"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7436835\/7202910.pdf?arnumber=7202910","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T02:34:43Z","timestamp":1633919683000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7202910\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":35,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2452910","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2016,4]]}}}