{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,10]],"date-time":"2026-01-10T00:58:28Z","timestamp":1768006708085,"version":"3.49.0"},"reference-count":85,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100000083","name":"Directorate for Computer and Information Science and Engineering through the National Science Foundation CAREER","doi-asserted-by":"publisher","award":["CCF-1054179"],"award-info":[{"award-number":["CCF-1054179"]}],"id":[{"id":"10.13039\/100000083","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/tvlsi.2015.2455874","type":"journal-article","created":{"date-parts":[[2015,8,18]],"date-time":"2015-08-18T18:39:08Z","timestamp":1439923148000},"page":"1266-1279","source":"Crossref","is-referenced-by-count":19,"title":["Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS"],"prefix":"10.1109","volume":"24","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7800-3269","authenticated-orcid":false,"given":"Yuxin","family":"Bai","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yanwei","family":"Song","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mahdi Nazm","family":"Bojnordi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alexander","family":"Shapiro","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eby G.","family":"Friedman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Engin","family":"Ipek","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403581"},{"key":"ref72","author":"bhatnagar","year":"2007","journal-title":"Advanced ASIC Chip Synthesis Using Synopsys Design Compiler Physical Compiler and PrimeTime"},{"key":"ref71","author":"jakushokas","year":"2010","journal-title":"Power Distribution Networks With On-Chip Decoupling Capacitors"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5653732"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2005.141"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2000.812601"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1007\/1-4020-8147-2_10"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/611817.611845"},{"key":"ref75","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1997.597223"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-95432-0_7"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277229"},{"key":"ref79","year":"2006","journal-title":"512Mb DDR2 SDRAM Component Data Sheet MT47H128M4B6-25"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.800533"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.35"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090651"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658654"},{"key":"ref37","first-page":"342","article-title":"A 0.27 V 30 MHz 17.7 nJ\/transform 1024-pt complex FFT core with super-pipelining","author":"seok","year":"2011","journal-title":"Proc ISSCC"},{"key":"ref36","first-page":"353","article-title":"A 9 GHz 65 nm Intel Pentium 4 processor integer execution core","author":"wijeratne","year":"2006","journal-title":"Proc ISSCC"},{"key":"ref35","article-title":"The microarchitecture of the Pentium 4 processor","author":"hinton","year":"2001","journal-title":"Intel Technol J"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/4.910495"},{"key":"ref60","article-title":"Verilator and systemperl","author":"snyder","year":"2004","journal-title":"Proc North Amer SystemC Users&#x2019; Group Design Autom Conf"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.33"},{"key":"ref61","year":"2014","journal-title":"Incisive Enterprise Simulator"},{"key":"ref63","first-page":"1","article-title":"SESC: SuperESCalar simulator","author":"ortego","year":"2004","journal-title":"Proc 17th Euro Micro Conf Real Time Syst (ECRTS)"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283808"},{"key":"ref64","year":"2011","journal-title":"45nm FreePDK Process Design Kit"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364663"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2004.07.014"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.37"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798233"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2007.913186"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"ref69","year":"2011","journal-title":"Synopsys's Design Compiler User Guide"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2217891"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"102","DOI":"10.1109\/LPE.2000.155261","article-title":"MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments","author":"musicer","year":"2000","journal-title":"Proc Int Symp Low Power Electron Design"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.853609"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1198684"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024947"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.5"},{"key":"ref23","first-page":"332","article-title":"Mitigating inductive noise in SMT processors","author":"el-essawy","year":"2004","journal-title":"Proc Int Symp Low Power Electron Design (ISLPED)"},{"key":"ref26","article-title":"Some limits of power delivery in the multicore era","author":"zhang","year":"2012","journal-title":"Proc WEED"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.1043335"},{"key":"ref50","first-page":"1","article-title":"Voltage noise: Why its bad, and what to do about it","author":"reddi","year":"2009","journal-title":"Proceedings of IEEE Workshop on Silicon Errors in Logic - System Effects"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/871656.859628"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"},{"key":"ref58","year":"2014","journal-title":"Floating Point Unit"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253188"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176261"},{"key":"ref55","author":"gray","year":"2001","journal-title":"Analysis and Design of Analog Integrated Circuits"},{"key":"ref54","article-title":"An analysis of MOS current mode logic for low power and high performance digital logic","author":"musicer","year":"2000"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2000.812603"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.104"},{"key":"ref10","article-title":"M7: Next generation SPARC","author":"phillips","year":"2014","journal-title":"Proc Hot Chips II Symp High Performance Chips"},{"key":"ref11","year":"2012","journal-title":"Intel Xeon Phi Product Family"},{"key":"ref40","doi-asserted-by":"crossref","first-page":"392","DOI":"10.1109\/ISCA.1995.524578","article-title":"Simultaneous multithreading: Maximizing on-chip parallelism","author":"tullsen","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"ref12","year":"2011","journal-title":"TilePro Processor Family"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/4.509864"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.804336"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/4.924861"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1995.524546"},{"key":"ref16","first-page":"iv-369","article-title":"Shunt-peaking in MCML gates and its application in the design of a 20 Gb\/s half-rate phase detector","author":"bui","year":"2004","journal-title":"Proc ISCAS"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306783"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2004.1329007"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.1177\/109434209100500306"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2003.811023"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1109\/99.660313"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2039258"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"ref4","year":"2005","journal-title":"Cray X1E supercomputer"},{"key":"ref3","article-title":"MOS current-mode logic standard cells for high-speed low-noise applications","author":"badel","year":"2008"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1147\/rd.353.0313"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1147\/rd.365.0829"},{"key":"ref85","doi-asserted-by":"publisher","DOI":"10.1023\/A:1009817804059"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.35"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2011.12.007"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCHMT.1981.1135787"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910967"},{"key":"ref46","author":"mezhiba","year":"2012","journal-title":"Power Distribution Networks in High Speed Integrated Circuits"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1023\/A:1015348708421"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-9260(00)00005-5"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878223"},{"key":"ref42","author":"salman","year":"2012","journal-title":"High Performance Integrated Circuits"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2006.264841"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2016614"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2011.09.003"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7436835\/7208871.pdf?arnumber=7208871","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,13]],"date-time":"2023-08-13T07:15:34Z","timestamp":1691910934000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7208871\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":85,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2455874","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,4]]}}}