{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,18]],"date-time":"2025-12-18T14:01:49Z","timestamp":1766066509052},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/tvlsi.2015.2459726","type":"journal-article","created":{"date-parts":[[2015,8,18]],"date-time":"2015-08-18T18:39:08Z","timestamp":1439923148000},"page":"1593-1597","source":"Crossref","is-referenced-by-count":15,"title":["Low-Energy Write Operation for 1T-1MTJ STT-RAM Bitcells With Negative Bitline Technique"],"prefix":"10.1109","volume":"24","author":[{"given":"Hooman","family":"Farkhani","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ali","family":"Peiravi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Farshad","family":"Moradi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2011.2169456"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2267754"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DRC.2011.5994447"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2239671"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2004.837608"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2275082"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2008.2003063"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2012.2234079"},{"key":"ref7","article-title":"Transmission gate-based spin-transfer torque memory unit","author":"chen","year":"2011"},{"key":"ref2","first-page":"33","article-title":"Spin-transfer torque MRAM (STT-MRAM): Challenges and prospects","volume":"18","author":"huai","year":"2008","journal-title":"AAPPS Bull"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333665"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2169678"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7436835\/7208896.pdf?arnumber=7208896","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T02:34:43Z","timestamp":1633919683000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7208896\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":12,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2459726","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,4]]}}}