{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:41:55Z","timestamp":1773247315897,"version":"3.50.1"},"reference-count":37,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001868","name":"National Science Council","doi-asserted-by":"publisher","award":["NSC 101-2628-E-009-013-MY3"],"award-info":[{"award-number":["NSC 101-2628-E-009-013-MY3"]}],"id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/tvlsi.2015.2464092","type":"journal-article","created":{"date-parts":[[2015,8,18]],"date-time":"2015-08-18T18:39:08Z","timestamp":1439923148000},"page":"1293-1304","source":"Crossref","is-referenced-by-count":33,"title":["A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory"],"prefix":"10.1109","volume":"24","author":[{"given":"Kin-Chu","family":"Ho","sequence":"first","affiliation":[]},{"given":"Chih-Lung","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Hsie-Chia","family":"Chang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2014.2339329"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2007.899516"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2006.887082"},{"key":"ref30","first-page":"1426","article-title":"Error floors of LDPC codes","author":"richardson","year":"2003","journal-title":"Proc 41st Annu Allerton Conf Commun Control Comput"},{"key":"ref37","first-page":"1","article-title":"Soft information for LDPC decoding in flash: Mutual-information optimized quantization","author":"wang","year":"2011","journal-title":"Proc IEEE Global Telecommun Conf (GLOBECOM)"},{"key":"ref36","first-page":"1","year":"2007"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.894409"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2265314"},{"key":"ref10","article-title":"High-efficiency SSD for reliable data storage systems","author":"yang","year":"0","journal-title":"Flash Memory Summit"},{"key":"ref11","first-page":"424","article-title":"Over- $10\\times $ -extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme","author":"tanakamaru","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"},{"key":"ref12","first-page":"222","article-title":"A 45 nm 6 b\/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine","author":"ho","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2010.091710.090721"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9781139172769"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2006.881361"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2008.060025"},{"key":"ref17","article-title":"Low-power error correction for mobile storage","author":"yang","year":"0","journal-title":"Flash Memory Summit"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2009.5325933"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2004.841982"},{"key":"ref28","first-page":"442","article-title":"A 159 mm2 32 nm 32 Gb MLC NAND-flash memory with 200 Mb\/s asynchronous DDR interface","author":"kim","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"},{"key":"ref4","first-page":"117","article-title":"Codes correcterus d&#x2019;erreurs","volume":"2","author":"hocquenghem","year":"1959","journal-title":"Chiffres"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511803253"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/S0019-9958(60)90287-4"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-60693-9_13"},{"key":"ref29","year":"0","journal-title":"ONFi 3 2"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1962.1057683"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/26.768759"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/18.748992"},{"key":"ref2","first-page":"218","article-title":"A 128 Gb 3 b\/cell NAND flash design using 20 nm planar-cell technology","author":"naso","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4234.1001666"},{"key":"ref1","first-page":"436","article-title":"128 Gb 3 b\/cell NAND flash memory in 19 nm technology with 18 Mb\/s write rate and 400 Mb\/s toggle mode","author":"li","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2006.880240"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2194176"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.817545"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2046964"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042255"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2215746"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2009.5117900"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7436835\/07208881.pdf?arnumber=7208881","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T02:34:44Z","timestamp":1633919684000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7208881\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":37,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2464092","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,4]]}}}