{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,27]],"date-time":"2025-07-27T07:38:21Z","timestamp":1753601901567},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"MediaTek Singapore Pte Ltd., Singapore"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/tvlsi.2015.2465841","type":"journal-article","created":{"date-parts":[[2015,8,21]],"date-time":"2015-08-21T18:50:40Z","timestamp":1440183040000},"page":"1430-1440","source":"Crossref","is-referenced-by-count":9,"title":["A Performance-Aware MOSFET Threshold Voltage Measurement Circuit in a 65-nm CMOS"],"prefix":"10.1109","volume":"24","author":[{"given":"Dong","family":"Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiao Liang","family":"Tan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pak Kwong","family":"Chan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/81.933328"},{"key":"ref32","author":"carusone","year":"2013","journal-title":"Analog Integrated Circuit Design"},{"key":"ref31","first-page":"2833","article-title":"A low noise, $1.28~\\mu $ A quiescent regulator with broadband high PSR for micropower sensors","author":"ong","year":"2012","journal-title":"Proc IEEE ISCAS"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.808328"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/4.982424"},{"key":"ref10","first-page":"332","article-title":"A sub-1 V bandgap voltage reference in 32 nm FinFET technology","author":"annema","year":"2009","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2021922"},{"key":"ref12","first-page":"278","article-title":"A 210 nW 29.3 ppm\/°C 0.7 V voltage reference with a temperature range of ?50 to 130 °C in $0.13~\\mu $ m CMOS","author":"lee","year":"2011","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2092997"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2195065"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2206683"},{"key":"ref16","first-page":"1","article-title":"A sub-1-V 65-nm MOS threshold monitoring-based voltage reference","volume":"pp","author":"tan","year":"2014"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-010-9572-7"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2340576"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2415292"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609253"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.991391"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/5.573737"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050532"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.806265"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/4.953485"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.806266"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.899077"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1093\/ietele\/e90-c.10.2044"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2008.4708753"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672187"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1587\/transele.E93.C.835"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2024663"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.815371"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/BF00896619"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.124"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884070"},{"key":"ref26","first-page":"4","article-title":"Impact of temperature fluctuations on circuit characteristics in 180 nm and 65 nm CMOS technologies","author":"kumar","year":"2006","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"396","DOI":"10.1145\/1278480.1278582","article-title":"characterizing process variation in nanometer cmos","author":"agarwal","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7436835\/7217840.pdf?arnumber=7217840","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T02:34:43Z","timestamp":1633919683000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7217840\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":35,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2465841","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,4]]}}}