{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,7]],"date-time":"2026-04-07T21:55:38Z","timestamp":1775598938273,"version":"3.50.1"},"reference-count":52,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2016,5,1]],"date-time":"2016-05-01T00:00:00Z","timestamp":1462060800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,5]]},"DOI":"10.1109\/tvlsi.2015.2488282","type":"journal-article","created":{"date-parts":[[2015,10,26]],"date-time":"2015-10-26T14:55:26Z","timestamp":1445871326000},"page":"1770-1782","source":"Crossref","is-referenced-by-count":7,"title":["CLAP: Clustered Look-Ahead Prefetching for Energy-Efficient DRAM System"],"prefix":"10.1109","volume":"24","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5047-3568","authenticated-orcid":false,"given":"Yebin","family":"Lee","sequence":"first","affiliation":[]},{"given":"Soontae","family":"Kim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/384286.264207"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.1993.92"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2008.13"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654102"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771792"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2005.195553"},{"key":"ref37","first-page":"25","article-title":"Skinflint DRAM system: Minimizing DRAM chip writes for low power","author":"lee","year":"2013","journal-title":"Proc IEEE 19th Int Symp High Perform Comput Archit"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000100"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.43"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815983"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/356989.356999"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658648"},{"key":"ref29","first-page":"5","article-title":"Design and implementation of power-aware virtual memory","author":"huang","year":"2003","journal-title":"Proc Annu Conf USENIX Annu Tech Conf"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2007.913724"},{"key":"ref1","author":"schmitz","year":"2004","journal-title":"System-Level Design Techniques for Energy-Efficient Embedded Systems"},{"key":"ref20","first-page":"-185v","article-title":"History-based memory mode prediction for improving memory performance","author":"park","year":"2003","journal-title":"Proc Int Symp Circuits Syst"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2011.31"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.108"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/12.966492"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/383082.383118"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903260"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012714"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669154"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2032916"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1145\/1210268.1210271"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/12.381947"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"209","DOI":"10.3233\/JEC-2009-0093","article-title":"Energy simulation of embedded XScale systems with XEEMU","volume":"3","author":"herczeg","year":"2009","journal-title":"J Embedded Comput"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/248209.237190"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.214"},{"key":"ref14","year":"2003","journal-title":"Intel 80200 Processor Based on Intel XScale Microarchitecture Developer's Manual"},{"key":"ref15","article-title":"CACTI 4.0","author":"tarjan","year":"2006"},{"key":"ref16","year":"2000","journal-title":"Design Compiler"},{"key":"ref17","author":"mudge","year":"2004","journal-title":"The Reference Manual for the Sim-Panalyzer Version 2 0"},{"key":"ref18","first-page":"1","article-title":"ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers","author":"kim","year":"2010","journal-title":"Proc IEEE 16th Int Symp High Perform Comput Archit"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.51"},{"key":"ref4","year":"2009","journal-title":"1Gb x16 x32 LPDDR SDRAM Datasheet—MT46H64M16LF-5 B"},{"key":"ref3","author":"jacob","year":"2010","journal-title":"Memory Systems Cache DRAM Disk"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508269"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.37"},{"key":"ref8","first-page":"7","article-title":"CSiBE benchmark: One year perspective and plans","author":"besz\u00e9des","year":"2004","journal-title":"Proc GCC Developers Summit"},{"key":"ref7","first-page":"3","article-title":"MiBench: A free, commercially representative embedded benchmark suite","author":"guthaus","year":"2001","journal-title":"Proc IEEE Int Workshop Workload Characterization"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346185"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1006\/jpdc.1996.0145"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1992.697004"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/125826.125932"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291034"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/142880.142891"},{"key":"ref42","first-page":"340","article-title":"A framework for data prefetching using off-line training of Markovian predictors","author":"kim","year":"2002","journal-title":"Proc IEEE Int Conf Comput Design VLSI Comput Process"},{"key":"ref41","first-page":"189","article-title":"Compiler orchestrated prefetching via speculation and predication","author":"rabbah","year":"2004","journal-title":"Proc 6th Int Conf Archit Support Program Lang Oper Syst"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1990.134547"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/356887.356892"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7456352\/7305830.pdf?arnumber=7305830","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:44:47Z","timestamp":1641987887000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7305830\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5]]},"references-count":52,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2488282","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,5]]}}}