{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:58:24Z","timestamp":1759147104852,"version":"3.37.3"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2016,5,1]],"date-time":"2016-05-01T00:00:00Z","timestamp":1462060800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100004837","name":"Spanish Ministerio de Ciencia e Innovaci\u00f3n","doi-asserted-by":"crossref","award":["TEC2011-27916","TEC2012-38558-C02-02"],"award-info":[{"award-number":["TEC2011-27916","TEC2012-38558-C02-02"]}],"id":[{"id":"10.13039\/501100004837","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100003359","name":"Generalitat Valenciana","doi-asserted-by":"publisher","award":["GV\/2014\/011"],"award-info":[{"award-number":["GV\/2014\/011"]}],"id":[{"id":"10.13039\/501100003359","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,5]]},"DOI":"10.1109\/tvlsi.2015.2493041","type":"journal-article","created":{"date-parts":[[2015,11,12]],"date-time":"2015-11-12T14:55:52Z","timestamp":1447340152000},"page":"1950-1961","source":"Crossref","is-referenced-by-count":16,"title":["High-Performance NB-LDPC Decoder With Reduction of Message Exchange"],"prefix":"10.1109","volume":"24","author":[{"given":"Jesus O.","family":"Lacruz","sequence":"first","affiliation":[]},{"given":"Francisco","family":"Garcia-Herrero","sequence":"additional","affiliation":[]},{"given":"Maria Jose","family":"Canet","sequence":"additional","affiliation":[]},{"given":"Javier","family":"Valls","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Digital Integrated Circuits A Design Perspective","year":"2003","author":"rabaey","key":"ref30"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2007.894088"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISIT.2008.4595129"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2190668"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2013.050813.120489"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2013.6810404"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2344113"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2354753"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2226920"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2071830"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2010.05.070096"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2046196"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4234.681360"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2047956"},{"year":"2006","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JPHOT.2012.2195777"},{"key":"ref29","doi-asserted-by":"crossref","first-page":"3430","DOI":"10.1109\/TCSI.2008.924892","article-title":"Algorithms of finding the first two minimum values and their hardware implementation","volume":"55","author":"wey","year":"2008","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1364\/OFC.2011.OWF4"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICC.2004.1312606"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ITW.2003.1216697"},{"year":"2004","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2013.2256905"},{"year":"2009","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISCIT.2007.4392200"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2362854"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2293224"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7169065"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2377194"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2009.06.070313"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"262","DOI":"10.1109\/TVLSI.2008.2002487","article-title":"Multi-Gb\/s LDPC code design and implementation","volume":"17","author":"sha","year":"2009","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7456352\/07328322.pdf?arnumber=7328322","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:44:47Z","timestamp":1641987887000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7328322\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5]]},"references-count":30,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2493041","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2016,5]]}}}